HMC1019LP4E 参数 Datasheet PDF下载

HMC1019LP4E

v00.0911

0.5 dB LSB GaAs MMIC 5-BIT DIGITAL

ATTENUATOR, 0.1 - 30 GHz

Timing Diagram

(Latched Asynchronous Mode)

Asynchronous Mode Truth Table

AsM1

High

AsM2

High

Low

High

Low

Attenuation State RF1-RF2

Reference I.L.

1.5 dB

14 dB

15.5 dB

AttenuAtors - DigitAl - sMt

High

Low

Low

Power-Up States

If LE is set to logic LOW at power-up, the logic state

of PUP determines the power-up state of the part per

PUP truth table. If the LE is set to logic HIGH at power-

up, the logic state of ASM1-ASM2 determines the

power-up state of the part per truth table for the asyn-

chronous mode. The attenuator latches in the desired

power-up state approximately 200 ms after power-up.

PUP Truth Table

PuP

High

Low

Attenuation State

Reference I.L.

15.5 dB

Note: The logic state of ASM1-ASM2 determines the

power-up state of the part per truth table for the asyn-

chronous mode when LE is high at power-up.

Bias Voltages & Currents

Vdd

Vdd1

Vss

+5V @ 0.2 mA

+5V @ 4.5 mA

-5V @ 5 mA

Control Voltage

State

Low

High

Bias Condition

0 to 0.8V @ 1 µA

2 to 5V @ 1 µA

5

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Phone: 978-250-3343

Fax: 978-250-3373

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