13.3.6 IRIC Set Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR and
ACK bit in ICCR. SCL is automatically held low after one frame has been transferred; this timing
is synchronized with the internal clock. Figure 13.10 shows the IRIC set timing and SCL control.
(a) When WAIT = 0 and ACK = 0
SCL
7
8
A
1
SDA
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
(b) When WAIT = 1 and ACK = 0
SCL
7
8
A
1
SDA
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
Note: The ICDR write (transmit) or read (receive) following the clearing of IRIC
should be executed after the rise of SCL (ninth clock pulse).
(c) When ACK = 1
SCL
SDA
IRIC
1
7
8
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
Figure 13.10 IRIC Set Timing and SCL Control
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HITACHI [ HITACHI SEMICONDUCTOR ]
