External Clock Input: The external clock signal should have the same frequency as the desired
system clock (ø). Clock timing parameters are given in table 6.7 and figure 6.12.
Table 6.7 Clock Timing
VCC = 3.0 to 5.5 V
Item
Symbol Min
Max
Unit
Test Conditions
Low pulse width of external
clock input
tEXL
40
—
ns
Figure 6.12
High pulse width of external tEXH
clock input
40
—
ns
External clock rise time
External clock fall time
tEXr
tEXf
tCL
—
10
ns
ns
tcyc
tcyc
tcyc
tcyc
—
10
Clock pulse
width low
0.3
0.4
0.3
0.4
0.7
0.6
0.7
0.6
ø ≥ 5 MHz
ø < 5 MHz
ø ≥ 5 MHz
ø < 5 MHz
Figure 23.7
Clock pulse
width high
tCH
tEXH
tEXL
EXTAL
VCC × 0.5
tEXr
tEXt
Figure 6.12 External Clock Input Timing
Table 6.8 lists the external clock output stabilization delay time. Figure 6.13 shows the timing for
the external clock output stabilization delay time. The oscillator and duty correction circuit have
the function of regulating the waveform of the external clock input to the EXTAL pin. When the
specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after
the elapse of the external clock output stabilization delay time (tDEXT). As clock signal output is not
confirmed during the tDEXT period, the reset signal should be driven low and the reset state
maintained during this time.
98
HITACHI [ HITACHI SEMICONDUCTOR ]
