82C55A
Ceramic Leadless Chip Carrier Packages (CLCC)
J44.A MIL-STD-1835 CQCC1-N44 (C-5)
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES MILLIMETERS
MIN
D3
SYMBOL
A
MAX
0.120
0.088
0.039
0.028
MIN
1.63
1.37
0.84
0.56
MAX
3.05
2.24
0.99
0.71
NOTES
o
j x 45
0.064
0.054
0.033
0.022
6, 7
A1
B
-
4
2, 4
-
B1
B2
B3
D
0.072 REF
1.83 REF
E3
E
B
0.006
0.640
0.022
0.662
0.15
0.56
-
16.26
16.81
-
D1
D2
D3
E
0.500 BSC
0.250 BSC
12.70 BSC
6.35 BSC
-
-
o
h x 45
-
0.662
0.662
-
16.81
16.81
2
-
0.010 S E F S
A1
0.640
16.26
E1
E2
E3
e
0.500 BSC
0.250 BSC
0.662
0.050 BSC
0.015
12.70 BSC
6.35 BSC
16.81
1.27 BSC
0.38
1.02 REF
0.51 REF
-
A
-
PLANE 2
PLANE 1
-
-
2
-
-E-
e1
h
-
-
2
5
5
-
0.040 REF
0.020 REF
j
0.007 M E F S H S
L
0.045
0.055
0.055
0.095
0.015
1.14
1.14
1.90
0.08
1.40
1.40
2.41
0.38
B1
L1
L2
L3
ND
NE
N
0.045
0.075
0.003
-
e
-
L3
L
-H-
-
11
11
44
11
11
44
3
3
3
-F-
Rev. 0 5/18/94
NOTES:
B3
E1
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
E2
B2
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
L1
D2
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
e1
D1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
26