82C55A
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
V
26
V
CC
CC
recommended for decoupling.
GND
7
GROUND
D0-D7
27-34
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET
CS
35
6
I
I
I
I
I
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
RD
5
READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WR
36
8, 9
WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
A0-A1
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PA0-PA7
1-4, 37-40
I/O
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PB0-PB7
PC0-PC7
18-25
10-17
I/O
I/O
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
Functional Diagram
I/O
PA7-PA0
+5V
GROUP A
PORT A
(8)
POWER
SUPPLIES
GND
GROUP A
CONTROL
GROUP A
PORT C
UPPER
(4)
I/O
PC7-PC4
BI-DIRECTIONAL
DATA BUS
DATA BUS
BUFFER
D7-D0
GROUP B
PORT C
LOWER
(4)
8-BIT
INTERNAL
DATA BUS
I/O
PC3-PC0
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-PB0
A0
RESET
CS
2
HARRIS [ HARRIS CORPORATION ]
