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MD82C55B 参数 Datasheet PDF下载

MD82C55B图片预览
型号: MD82C55B
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS可编程外设接口 [CMOS Programmable Peripheral Interface]
分类和应用:
文件页数/大小: 26 页 / 236 K
品牌: HARRIS [ HARRIS CORPORATION ]
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82C55A  
tST  
STB  
IBF  
tSIB  
tSIT  
tRIB  
INTR  
RD  
tRIT  
tPH  
INPUT FROM  
PERIPHERAL  
tPS  
FIGURE 7. MODE 1 (STROBED INPUT)  
INTE A  
INTR (Interrupt Request)  
A “high” on this output can be used to interrupt the CPU Controlled by Bit Set/Reset of PC6.  
when and input device is requesting service. INTR is set by  
INTE B  
the condition: STB is a “one”, IBF is a “one” and INTE is a  
“one”. It is reset by the falling edge of RD. This procedure  
allows an input device to request service from the CPU by  
simply strobing its data into the port.  
Controlled by Bit Set/Reset of PC2.  
NOTE:  
1. To strobe data into the peripheral device, the user must operate  
the strobe line in a hand shaking mode. The user needs to send  
OBF to the peripheral device, generates an ACK from the pe-  
ripheral device and then latch data into the peripheral device on  
the rising edge of OBF.  
INTE A  
Controlled by bit set/reset of PC4.  
INTE B  
MODE 1 (PORT A)  
Controlled by bit set/reset of PC2.  
8
PA7-PA0  
PC7  
CONTROL WORD  
Output Control Signal Definition  
D7 D6 D5 D4 D3 D2 D1 D0  
OBFA  
ACKA  
(Figure 8 and 9)  
1
0
1
1
1/0  
INTE  
A
PC6  
OBF - Output Buffer Full F/F). The OBF output will go “low”  
to indicate that the CPU has written data out to be specified  
port. This does not mean valid data is sent out of the part at  
this time since OBF can go true before data is available.  
Data is guaranteed valid at the rising edge of OBF, (See  
Note 1). The OBF F/F will be set by the rising edge of the  
WR input and reset by ACK input being low.  
PC4, PC5  
1 = INPUT  
0 = OUTPUT  
INTRA  
PC3  
2
WR  
PC4, PC5  
ACK - Acknowledge Input). A “low” on this input informs the  
82C55A that the data from Port A or Port B is ready to be  
accepted. In essence, a response from the peripheral device  
indicating that it is ready to accept data, (See Note 1).  
MODE 1 (PORT B)  
PB7-PB0  
8
CONTROL WORD  
D7 D6 D5 D4 D3 D2 D1 D0  
OBFB  
ACKB  
PC1  
INTR - (Interrupt Request). A “high” on this output can be  
used to interrupt the CPU when an output device has  
accepted data transmitted by the CPU. INTR is set when  
ACK is a “one”, OBF is a “one” and INTE is a “one”. It is  
reset by the falling edge of WR.  
1
1
0
INTE  
PC2  
B
INTRB  
PC0  
WR  
FIGURE 8. MODE 1 OUTPUT  
9
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