HSP3824
Control Port
External Interfaces
There are three primary digital interface ports for the The serial control port is used to serially write and read data to/
HSP3824 that are used for configuration and during normal from the device. This serial port can operate up to a 10MHz
operation of the device. These ports are:
rate or the maximum master clock rate of the device, MCLK
(whichever is lower). MCLK must be running and RESET inac-
tive during programming. This port is used to program and to
read all internal registers. The first 8 bits always represent
the address followed immediately by the 8 data bits for that
register. The two LSBs of address are don’t care. The serial
transfers are accomplished through the serial data pin (SD).
SD is a bidirectional serial data bus. An Address Strobe (AS),
Chip Select (CS), and Read/Write (R/W) are also required as
handshake signals for this port. The clock used in conjunction
with the address and data on SD is SCLK. This clock is pro-
vided by the external source and it is an input to the
HSP3824. The timing relationships of these signals are illus-
trated on Figure 3 and 4. AS is active high during the clock-
ing of the address bits. R/W is high when data is to be read,
and low when it is to be written. CS must be active (low) dur-
ing the entire data transfer cycle. CS selects the device. The
serial control port operates asynchronously from the TX and
RX ports and it can accomplish data transfers independent
of the activity at the other digital or analog ports. CS does
not effect the TX or RX operation of the device; impacting
only the operation of the Control port. The HSP3824 has 57
internal registers that can be configured through the control
port. These registers are listed in the Configuration and Con-
trol Internal Register table. Table 1 lists the configuration reg-
ister number, a brief name describing the register, and the
HEX address to access each of the registers. The type indi-
cates whether the corresponding register is Read only (R) or
Read/Write (R/W). Some registers are two bytes wide as
indicated on the table (high and low bytes).
• The TX Port, which is used to accept the data that needs
to be transmitted from the network processor.
• The RX Port, which is used to output the received demod-
ulated data to the network processor.
• The Control Port, which is used to configure, write and/or
read the status of the internal HSP3824 registers.
In addition to these primary digital interfaces the device
includes a byte wide parallel Test Port which can be configured
to output various internal signals and/or data (i.e. PN acquisi-
tion indicator, Correlator magnitude output etc.). The device can
also be set into various power consumption modes by external
control. The HSP3824 contains three Analog to Digital (A/D)
converters. The analog interfaces to the HSP3824 include, the
In phase (I) and quadrature (Q) data component inputs, and the
RF signal strength indicator input. A reference voltage divider is
also required external to the device.
HSP3824
I (ANALOG)
ANALOG
Q (ANALOG)
TXD
INPUTS
RSSI (ANALOG) TXCLK
TX_PORT
RX_PORT
TX_RDY
VREFN
RXD
A/D
REFERENCE
VREFP
RXC
MD_RDY
CS
TX_PE
RX_PE
RESET
POWER
DOWN
SIGNALS
SD
SCLK
R/W
CONTROL_PORT
8
TEST
PORT
TEST
AS
FIGURE 2. EXTERNAL INTERFACES
FIRST ADDRESS BIT IN
FIRST DATABIT OUT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
SCLK
SD
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
MSB
ADDRESS IN
MSB
DATA OUT
LSB
AS
R/W
CS
NOTE: Using falling edge SCLK to generate address/control and capture read data.
FIGURE 3. CONTROL PORT READ TIMING
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
SCLK
SD
AS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
ADDRESS IN
MSB
DATA IN
LSB
R/W
CS
NOTE: Using falling edge SCLK to generate address/control and data.
FIGURE 4. CONTROL PORT WRITE TIMING
7
HARRIS [ HARRIS CORPORATION ]
