HSP3824
The suggested method of optimization is to set the transmit- Secondly, when the bits are processed by the descrambler,
ter in a continuous transmit mode. Then, measure the time these errors are further extended. The descrambler is a 7-bit
until the receiver drops lock at low signal to noise ratio. Each shift register with one or more taps exclusive ored with the
of the 2 thresholds should be set individually to the same bit stream. If for example the scrambler polynomial uses 2
drop lock time. While setting thresholds for one of the signal taps that are summed with the data, then each error is
qualities the other should be configured at its limit so it does extended by a factor of three. Since the DPSK errors are
not influence the drop lock decisions. Set CR 26 to 00h while close together, however, some of them can be canceled in
determining the value of CR 34 and 35 for phase error the descrambler. In this case, two wrongs do make a right,
threshold. Set CR 34 to FFh while determining the value of so the observed errors can be in groups of 4 instead of 6.
CR 26 and 27 for bit sync. amplitude threshold.
Descrambling is done by a polynomial division using a pre-
Assuming a 10e-6 BER operating point, it is suggested that scribed polynomial. A shift register holds the last quotient and
the drop lock thresholds are set at 10e-3 BER, with each the output is the exclusive-or of the data and the sum of taps in
threshold adjusted individually.
the shift register. The taps and seed are programmable. The
transmit scrambler seed is programmed by CR 15 and the taps
are set with CR 16. One reason for setting the seed is that it
can be used to make the SFD scrambling the same every
packet so that it can be recognized in its scrambled state.
Note that the bit sync amplitude is linearly proportional to the
signal amplitude at the ADC converters. If an AGC system is
being used instead of a limiter, the bit sync amplitude thresh-
old should be set at or below the minimum amplitude that the
radio will see at its sensitivity level.
Demodulator Performance
Data Decoder and Descrambler
Description
This section indicates the theoretical performance and typi-
cal performance measures for a radio design. The perfor-
mance data below should be used as a guide. The actual
performance depends on the application, interference envi-
ronment, RF/IF implementation and radio component selec-
tion in general.
The data decoder that implements the desired DQPSK cod-
ing/decoding as shown in DQPSK Data Decoder Table 9.
This coding scheme results from differential coding of the
dibits. When used in the DBPSK modes, only the 00 and 11
dibits are used. Vector rotation is counterclockwise.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data demodula-
tion. Figure 18 below shows the performance of the base-
band processor when used in conjunction with the HSP3724
IF limiter and the PRISM recommended IF filters. Off the
shelf test equipment are used for the RF processing. The
curves should be used as a guide to assess performance in
a complete implementation.
TABLE 9. DQPSK DATA DECODER
PHASE SHIFT
DIBITS
00
0
+90
+180
-90
01
11
10
The data scrambler and de-scrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler can be dis-
abled for measuring RF carrier suppression. The scrambler
is designed to insure smearing of the discrete spectrum lines
produced by the PN code.
Factors for carrier phase noise, multipath, and other degra-
dations will need to be considered on an implementation by
implementation basis in order to predict the overall perfor-
mance of each individual system.
Figure 18 shows the curve for theoretical DBPSK/DQPSK
demodulation with coherent demodulation as well as the
PRISM performance measured for DBPSK and DQPSK. The
losses include RF and IF radio losses; they do not reflect the
HSP3824 losses alone. These are more realistic measure-
ments. The HSP3824 baseband losses from theoretical by
themselves are a small percentage of the overall loss.
One thing to keep in mind is that both the differential decod-
ing and the descrambling when used cause error extension.
This causes the errors to occur in groups of 4 and 6. This is
due to two properties of the processing. First, the differential
decoding process causes errors to occur in pairs. When a
symbol error is made, it is usually a single bit error even in
QPSK mode. When a symbol is in error, the next symbol will
also be decoded wrong since the data is encoded in the
change from one symbol to the next. Thus, two errors are
made on two successive symbols. In QPSK mode, these
may be next to one another or separated by up to 2 bits.
The PRISM demodulator performs at less than 3dB from the-
oretical in a AWGN environment with low phase noise local
oscillators. The observed errors occurred in groups of 4 and 6
errors and rarely singly. This is because of the error extension
properties of differential decoding and descrambling.
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