HSP3824
channel was last clear. If a source of interference makes it machine has four basic states. The first state clears the CCA
look like the channel is occupied, the circuit will detect a sig- when both the CS and ED are inactive. This indicates that
nal without carrier and will wait a proscribed time before the channel is truly clear.
deciding to transmit over the interference.
The second state sets the CCA to BUSY when the CS is
The receive signal strength indication (RSSI) measurement active and the ED is inactive. This corresponds to a channel
is an analog input to the HSP3824 from the successive IF where the signal just went away or dropped below threshold
stage of the radio. The RSSI ADC converts it within the but the carrier is still being sensed. The third state sets the
baseband processor and it compares it to a programmable CCA to BUSY and resets the cycle counter when the ED and
threshold. This threshold is normally set to between -70 and CS are both active. This is an obviously busy channel.
-80dBm. This measure is used in the acquisition decision
The fourth state increments the cycle counter if the CS is
and is also passed to the clear channel assessment logic.
inactive and the ED is active, and sets the CCA to BUSY if
The state diagram in Figure 13 shows the operation of the
the count is less than N. This is where the channel has just
clear channel assessment state machine.
had a new signal come up and the carrier has not yet been
The energy detection (ED) signal is the digitized RSSI signal. acquired or where an interferer turns on.
The carrier sense (CS) input is derived from a combination of
If the cycle counter reaches N, the counter is reset and the
the Signal Quality 2 (SQ2) based on phase error and the Sig-
CCA is set to CLEAR. This happens on interference that per-
nal Quality 1(SQ1) based on PN correlator magnitude out-
sists. If the channel has interference, it may be low enough
puts. Both Signal Quality measures and the ED input are
to allow communications. The CCA state machine does
differentiated to sense when they change. These change
not influence any of the receive or transmit operations
detectors and the watchdog timer TIME OUT output are com-
within the HSP3824. The CCA algorithm output is an
bined to initiate a clear channel assessment decision.
indication to the network processor. The processor can
The CCA algorithm will always declare the channel busy if ignore this indicator and decide to have the HSP3824
CS is active. If only ED is active the state machine will ini- transmit regardless of the state of CCA.
tially declare a busy channel and at the same time it will start
The Configuration registers effecting the CCA algorithm
timing ED until it meets the programmed time out count.
operation are summarized below (more programming details
When the time out expires the state machine will declare the
on these registers can be found under the Control Registers
channel as being clear even if the ED is still active. This will
section of this document).
prevent the transmitter locking out permanently on some
persisting interference. This time out period is programmable
by 2 parameters that define an inner count M and an outer
count N. The total time out period is determined by the time
corresponding to the product of MxN. The value of the inner
counter M is programmable through CR 17 while the value of
the outer counter N is programmable through CR 18. The
state machine cycles M times the N count before it asserts
CCA, declaring the channel as clear for transmission. Note
that the counters are automatically reset to restart the count
when CS is detected to be active. In summary the CCA state
The CCA output from pin 32 of the device can be defined as
active high or active low through CR 9 (bit 5). The RSSI
threshold is set through CR19. If the actual RSSI value from
the ADC exceeds this threshold then ED becomes active.
The instantaneous RSSI value can be monitored by the exter-
nal network processor by reading CR 10. The programmable
thresholds on the two signal quality measurements are set
through CR22, 23, 30, and 31. Signal Quality 1 and 2 thresh-
olds derive the state of the Carrier Sense. More details on SQ
are included under the receiver section of this document.
A/D
SECTION
CORRELATOR
16TAP
I
SIGNAL QUALITY 1
MAGNITUDE AND
SYMBOL
TIMING
PHASE DISTRIBUTION
A/D
SECTION
CORRELATOR
16TAP
Q
SYMBOL TIMING
PHASE
ROTATE
PSK
DEMOD
DIF
DEC
DATA
DESCRAM
TIMING
CONTROL
RXD
PHASE
ERROR
AVG
PHASE
ERROR
SIGNAL QUALITY 2
ABS
AVG
PHASE
FREQ.
LEAD
/LAG
NCO
FILTER
FIGURE 14. DEMODULATOR BLOCK DIAGRAM
19
HARRIS [ HARRIS CORPORATION ]
