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HSP3824 参数 Datasheet PDF下载

HSP3824图片预览
型号: HSP3824
PDF下载: 下载PDF文件 查看货源
内容描述: 直接序列扩频基带处理器 [Direct Sequence Spread Spectrum Baseband Processor]
分类和应用:
文件页数/大小: 41 页 / 278 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HSP3824  
TABLE 3. ADC CALIBRATION  
CR 1 ADC CALIBRATION CIRCUIT  
The procedure for setting the ADC references to accommo-  
date various input signal voltage levels is to set the reference  
voltages so that the ADC calibration circuit is operating at  
half scale. This leaves the maximum amount of adjustment  
room for circuit tolerances.  
CR 1  
BIT 0  
BIT 1  
CONFIGURATION  
Automatic real time adjustment of reference.  
Reference set at mid scale.  
0
0
1
1
0
1
0
1
Figure 8 illustrates the suggested interface configuration for  
the ADCs and the reference circuits.  
Reference held at most recent value.  
Reference set at mid scale.  
I
IIN  
0.01µF  
0.01µF  
RSSI ADC Interface  
Q
QIN  
The Receive Signal Strength Indication (RSSI) analog signal is  
input to a 6-bit ADC, indicating 64 discrete levels of received  
signal strength. This ADC measures a DC voltage, so its input  
must be DC coupled. Pin 16 (VREFP) sets the reference for the  
RSSI ADC converter. VREFP is common for the I and Q and  
RSSI ADCs. The RSSI signal is used as an input to the pro-  
grammable Clear Channel Assessment algorithm of the  
HSP3824. The RSSI ADC output is stored in an 8-bit register  
(CR10) and it is updated at the symbol rate for access by the  
external processor to assist in network management.  
3.9K  
2V  
VREFP  
0.01µF  
0.01µF  
8.2K  
9.1K  
VREFN  
HSP3824  
FIGURE 8. INTERFACES  
The interface specifications for the RSSI ADC are listed on  
Table 4 below (VREFP = 1.75V).  
ADC Calibration Circuit and Registers  
The ADC compensation or calibration circuit is designed to  
optimize ADC performance for the I and Q inputs by main-  
taining the full 3-bit resolution of the outputs. There are two  
registers (CR 11 AD_CAL_POS and CR 12 AD_CAL_NEG)  
that set the parameters for the internal I and Q ADC calibra-  
tion circuit.  
TABLE 4. RSSI ADC SPECIFICATIONS  
PARAMETER  
Full Scale Input Voltage  
Input Bandwidth (0.5dB)  
Input Capacitance  
MIN  
TYP  
MAX  
-
1MHz  
-
-
1.15  
-
7pF  
-
-
-
-
Input Impedance (DC)  
1M  
Both I and Q ADC outputs are monitored by the ADC calibra-  
tion circuit and if either has a full scale value, a 24-bit accu-  
mulator is incremented as defined by parameter  
AD_CAL_POS. If neither has a full scale value, the accumu-  
lator is decremented as defined by parameter  
AD_CAL_NEG.  
Test Port  
The HSP3824 provides the capability to access a number of  
internal signals and/or data through the Test port, pins TEST  
0-7. In addition pin 1 (TEST_CK) is an output clock that can  
be used in conjunction with the data coming from the test  
port outputs. The test port is programmable through configu-  
ration register (CR5).  
A loop gain reduction is accomplished by using only the 5  
MSBs out of the 24 bits to drive a D/A converter that adjusts  
the ADCs reference. The compensation adjustment is  
updated at 2kHz rate for a 2 MBPS operation. The ADC cali-  
bration circuit is only intended to remove slow component  
variations.  
There are 9 test modes assigned to the PRISM test port  
listed in the Test Modes Table 5.  
TABLE 5. TEST MODES  
The ratio of the values from the two registers CR11 and  
CR12 set the probability that either the I or Q ADC converter  
will be at the saturation. The probability is set by  
(AD_CAL_POS)/(AD_CAL_NEG).  
MODE DESCRIPTION TEST_CLK  
TEST (7:0)  
0
1
2
3
Normal  
Operation  
TXCLK  
CRS, ED, “000”, Initial  
Detect, Reserved (1:0)  
Correlator Test  
Mode  
TXCLK  
Mag (7:0)  
This also sets the levels so that operation with either NOISE  
or DPSK is approximately the same. It is assumed that the  
RF and IF sections of the receiver have enough gain to  
cause limiting on thermal noise. This will keep the levels at  
the ADC approximately same regardless of whether signal is  
present or not.  
Frequency Test DCLK  
Mode  
Frq Reg (7:0)  
Phase Test  
Mode  
DCLK  
Phase (7:0)  
4
5
NCO Test Mode DCLK  
NCO Phase Accum Reg  
SQ Test Mode  
LoadSQ  
SQ2 (15:8) Phase  
Variance  
The ADC calibration voltage is automatically held during  
transmit in half duplex operation.  
6
7
Bit Sync Test  
Mode 1  
RXCLK  
Bit Sync Accum (7:0)  
The ADC calibration circuit operation can be defined through  
CR 1, bits 1 and 0. Table 3 illustrates the possible  
configurations.  
Bit Sync Test  
Mode 2  
LoadSQ  
SQ (14:7) Bit Sync Ref-  
Data  
12