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HSP3824 参数 Datasheet PDF下载

HSP3824图片预览
型号: HSP3824
PDF下载: 下载PDF文件 查看货源
内容描述: 直接序列扩频基带处理器 [Direct Sequence Spread Spectrum Baseband Processor]
分类和应用:
文件页数/大小: 41 页 / 278 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HSP3824  
I/Q ADC Interface  
RX Port  
The timing diagram Figure 7 illustrates the relationships The PRISM baseband processor chip (HSP3824) includes  
between the various signals of the RX port. The receive data two 3-bit Analog to Digital converters (ADCs) that sample  
port serially outputs the demodulated data from RXD. The the analog input from the IF down converter. The I/Q ADC  
data is output as soon as it is demodulated by the HSP3824. clock, MCLK, samples at twice the chip rate. The maximum  
RX_PE must be at its active state throughout the receive sampling rate is 44MHz (power supply: 3.3V to 5.0V) or  
operation. When RX_PE is inactive the device's receive 33MHz (power supply 2.7V to 5.5V).  
functions, including acquisition, will be in a stand by mode.  
The interface specifications for the I and Q ADCs are listed  
on Table 2 below.  
RXCLK is an output from the HSP3824 and is the clock for  
the serial demodulated data on RXD. MD_RDY is an output  
from the HSP3824 and it envelopes the valid data on RXD.  
The HSP3824 can be also programmed to ignore error  
detections during the CCITT - CRC 16 check of the header  
fields. If programmed to ignore errors the device continues to  
output the demodulated data in its entirety regardless of the  
CCITT - CRC 16 check result. This option is programmed  
through CR 2, bit 5.  
TABLE 2. I, Q, ADC SPECIFICATIONS  
PARAMETER  
MIN  
TYP  
MAX  
Full Scale Input Voltage (V  
Input Bandwidth (-0.5dB)  
Input Capacitance (pF)  
Input Impedance (DC)  
)
0.25  
0.50  
1.0  
P-P  
-
20MHz  
-
-
5k  
-
5
-
-
-
FS (Sampling Frequency)  
-
44MHz  
Note that RXCLK becomes active after acquisition, well  
before valid data begins to appear on RXD and MD_RDY is  
asserted. MD_RDY returns to its inactive state under the fol-  
lowing conditions:  
The voltages applied to pin 16,VREFP and pin 17, VREFN set  
the references for the internal I and Q ADC converters. In  
addition, VREFP is also used to set the RSSI ADC converter  
reference. For a nominal 500mVP-P, the suggested VREFP  
voltage is 1.75V, and the suggested VREFN is 0.93V. VREFN  
should never be less than 0.25V. Since these ADCs are  
intended to sample AC voltages, their inputs are biased  
internally and they should be capacitively coupled.  
• The number of data symbols, as defined by the length field  
in the protocol, has been received and output through  
RXD in its entirety (normal condition).  
• PN tracking is lost during demodulation.  
• RX_PE is deactivated by the external controller.  
The ADC section includes a compensation (calibration) cir-  
cuit that automatically adjusts for temperature and compo-  
nent variations of the RF and IF strips. The variations in gain  
of limiters, AGC circuits, filters etc. can be compensated for  
up to ±4dB. Without the compensation circuit, the ADCs  
could see a loss of up to 1.5 bits of the 3 bits of quantization.  
The ADC calibration circuit adjusts the ADC reference volt-  
ages to maintain optimum quantization of the IF input over  
this variation range. It works on the principle of setting the  
reference to insure that the signal is at full scale (saturation)  
a certain percentage of the time. Note that this is not an  
AGC and it will compensate only for slow variations in signal  
levels (several seconds).  
MD_RDY can be configured through CR 9, bit 6 to be active  
low, or active high. Energy Detect (ED) pin 45 (Test port),  
and Carrier Sense (CRS) pin 46 (Test port), are available  
outputs from the HSP3824 and can be useful signals for an  
effective RX interface design. Use of these signals is  
optional. CRS and ED are further described within this docu-  
ment. The receive port is completely independent from the  
operation of the other interface ports including the TX port,  
supporting therefore a full duplex mode.  
RXCLK  
RX_PE  
CRS (TEST 7)  
PROCESSING  
PREAMBLE/HEADER  
MD_RDY  
RXD  
LSB  
DATA  
MSB  
NOTE: MD_RDY active after CRC16.  
FIGURE 7. RX PORT TIMING  
11