82C37A
Functional Description
The 82C37A direct memory access controller is designed to For example, if a block of data is to be transferred from RAM
improve the data transfer rate in systems which must to an I/O device, the starting address of the data is loaded
transfer data from an I/O device to memory, or move a block into the 82C37A Current and Base Address registers for a
of memory to an I/O device. It will also perform memory-to- particular channel, and the length of the block is loaded into
memory block moves, or fill a block of memory with data the channel’s Word Count register. The corresponding Mode
from a single location. Operating modes are provided to register is programmed for a memory-to-I/O operation (read
handle single byte transfers as well as discontinuous data transfer), and various options are selected by the Command
streams, which allows the 82C37A to control data movement register and the other Mode register bits. The channel’s
with software transparency.
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
software command.
The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without Once initiated, the block DMA transfer will proceed as the
ever being stored in a temporary register. This can greatly controller outputs the data address, simultaneous MEMR
increase the data transfer rate for sequential operations, and IOW pulses, and selects an I/O device via the DMA
compared with processor move or repeated string acknowledge (DACK) outputs. The data byte flows directly
instructions.
Memory-to-memory
operations
require from the RAM to the I/O device. After each byte is
temporary internal storage of the data byte between transferred, the address is automatically incremented (or
generation of the source and destination addresses, so decremented) and the word count is decremented. The
memory-to-memory transfers take place at less than half the operation is then repeated for the next byte. The controller
rate of I/O operations, but still much faster than with central stops transferring data when the Word Count register
processor techniques. The maximum data transfer rates underflows, or an external EOP is applied.
obtainable with the 82C37A are shown in Figure 1.
NAME
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
SIZE
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
8-Bits
NUMBER
The block diagram of the 82C37A is shown on page 2. The
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from clock input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.
4
4
4
4
1
1
1
1
1
4
1
1
82C37A
TRANSFER
TYPE
Compressed
Normal I/O
5MHz
2.50
1.67
0.63
8MHz
4.00
2.67
1.00
12.5MHz
6.25
UNIT
MByte/sec
MByte/sec
MByte/sec
Command Register
8-Bits
4.17
Temporary Register
8-Bits
Memory-to-
Memory
1.56
Mode Registers
6-Bits
FIGURE 1. DMA TRANSFER RATES
Mask Register
4-Bits
DMA Operation
Request Register
4-Bits
In a system, the 82C37A address and control outputs and
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C37A
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously
been programmed into the controller via the Command,
Mode, Address, and Word Count registers.
FIGURE 2. 82C37A INTERNAL REGISTERS
To further understand 82C37A operation, the states
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, active and idle.
After being programmed, the controller is normally idle until
a DMA request occurs on an unmasked channel, or a
software request is given. The 82C37A will then request
control of the system busses and enter the active cycle. The
active cycle is composed of several internal states,
depending on what options have been selected and what
type of operation has been requested.
4-196
HARRIS [ HARRIS CORPORATION ]
