HANBit
HMS12832M4
( /OE Low Fixed )
TIMING WAVEFORM OF WRITE CYCLE
tWC
Address
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tOH
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tWHZ(6,7)
tOW
(10)
(9)
High-Z(8)
Data Out
(Write Cycle)
Notes
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When /CE is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
H
/WE
X*
H
/OE
X
MODE
Not Select
Output Disable
Read
I/O PIN
High-Z
High-Z
DOUT
SUPPLY CURRENT
l SB, l SB1
lCC
L
H
L
H
L
lCC
L
L
X
Write
DIN
lCC
Note: X means Don't Care
7
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HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
