欢迎访问ic37.com |
会员登录 免费注册
发布采购

HMNR328DV-85I 参数 Datasheet PDF下载

HMNR328DV-85I图片预览
型号: HMNR328DV-85I
PDF下载: 下载PDF文件 查看货源
内容描述: 5.0或3.3V , 256K位( 32千位×8 ) TIMEKEEPER NVSRAM [5.0 or 3.3V, 256K bit (32 Kbit x 8) TIMEKEEPER NVSRAM]
分类和应用: 静态存储器
文件页数/大小: 13 页 / 302 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
 浏览型号HMNR328DV-85I的Datasheet PDF文件第5页浏览型号HMNR328DV-85I的Datasheet PDF文件第6页浏览型号HMNR328DV-85I的Datasheet PDF文件第7页浏览型号HMNR328DV-85I的Datasheet PDF文件第8页浏览型号HMNR328DV-85I的Datasheet PDF文件第9页浏览型号HMNR328DV-85I的Datasheet PDF文件第11页浏览型号HMNR328DV-85I的Datasheet PDF文件第12页浏览型号HMNR328DV-85I的Datasheet PDF文件第13页  
HANBit  
HMNR328D(V)  
Register Map  
Funtion /  
Data  
Address  
Range BCD Format  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
7FFF  
7FFE  
7FFD  
7FFC  
7FFB  
7FFA  
7FF9  
7FF8  
7FF7  
7FF6  
7FF5  
7FF4  
7FF3  
7FF2  
7FF1  
7FF0  
10Years  
Year  
Year  
Month  
Date  
00-99  
01-12  
01-31  
01-07  
00-23  
00-59  
00-59  
0
0
0
0
0
10M  
0
Month  
Date : Day of Month  
Day  
10 Date  
0
FT  
0
0
0
Day  
0
10 Hours  
10 Minutes  
Hours(24 Hour Format)  
Minutes  
Hours  
Minutes  
Seconds  
Control  
0
ST  
W
0
10 Seconds  
Seconds  
R
0
0
0
0
0
0
S
0
0
0
0
0
0
Calibration  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1000 Years  
100 Years  
Century  
Flag  
00-99  
0
0
0
BL  
0
0
0
0
Keys :  
R = READ Bit  
W = WRITE Bit  
ST = Stop Bit  
0 = Must be set to 0’  
BL = Battery Low Flag  
S = Sign Bit  
CLOCK OPERATIONS  
The HMNR328D(V) offers 16 internal registers which contain TIMEKEEPER, and Control data. These registers are  
memory locations which contain external (user accessible) and internal copies of the data. The external copies are  
independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented  
internal copy. TIMEKEEPER Registers store data in BCD. Control Registers store data in Binary Format.  
Reading the Clock  
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition.  
The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the  
registers can be halted without disturbing the clock itself. Updating is halted when a 1is written to the READ Bit, D6 in the  
Control Register (7FF8h). As long as a 1remains in that position, updating is halted. After a halt is issued, the registers  
reflect the count; that is, the day, date, and time that were current at the moment the halt command was is-sued. All of the  
TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs  
approximately 1 second after the READ Bit is reset to a 0.’  
URL : www.hbe.co.kr  
10  
HANBit Electronics Co.,Ltd.  
Rev. 0.0 (January, 2002)  
 复制成功!