HANBit
HMNR28D(V)
Register Map
Funtion /
Data
Address
Range BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
7FF
7FE
7FD
7FC
7FB
7FA
7F9
7F8
7F7
7F6
7F5
7F4
7F3
7F2
7F1
7F0
10Years
Year
Year
Month
Date
00-99
0
0
0
0
0
10M
0
Month
Date : Day of Month
Day
01-12
01-31
01-07
00-23
00-59
00-59
10 Date
0
FT
0
0
0
Day
0
10 Hours
10 Minutes
Hours(24 Hour Format)
Minutes
Hours
Minutes
Seconds
Control
0
ST
W
0
10 Seconds
Seconds
R
0
0
0
0
0
0
S
0
0
0
0
0
0
Calibration
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1000 Years
100 Years
Century
Flag
00-99
0
0
0
BL
0
0
0
0
Keys :
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to ’0’
BL = Battery Low Flag
S = Sign Bit
CLOCK OPERATIONS
The HMNR28D(V) offers 16 internal registers which contain TIMEKEEPER, and Control data. These registers are memory
locations which contain external (user accessible) and internal copies of the data. The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy.
TIMEKEEPER Registers store data in BCD. Control Registers store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition.
The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the
registers can be halted without disturbing the clock itself. Updating is halted when a ’1’ is written to the READ Bit, D6 in the
Control Register (7F8h). As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the registers
reflect the count; that is, the day, date, and time that were current at the moment the halt command was is-sued. All of the
TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs
approximately 1 second after the READ Bit is reset to a ’0.’
URL : www.hbe.co.kr
Rev. 0.0 (March, 2002)
10
HANBit Electronics Co.,Ltd.