HANBit
HMN1288D
POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP.
MAX
UNIT
㎲
㎲
VCC slew, 4.75 to 4.25V
tPF
300
-
-
VCC slew, 4.75 to VSO
tFS
tPU
10
0
-
-
-
-
㎲
VCC slew, VSO to VPFD (max)
Time during which SRAM
is write-protected after VCC
passes VPFD on power-up.
Chip enable recovery time
tCER
40
10
40
80
-
120
-
ms
Data-retention time in
Absence of VCC
TA = 25℃
tDR
years
Delay after VCC slew’s down
past VPFD before SRAM is
Write-protected.
㎲
Write-protect time
tWPT
100
150
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*1,2
Address
tACC
tOH
Previous Data Valid
DOUT
Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
tRC
CE
tACE
tCHZ
tCLZ
DOUT
High-Z
High-Z
URL : www.hbe.co.kr
Rev. 1.0 (June, 2002)
6
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
