GS882ZV18/36BB/D-333/300/250/200
GS882ZV18/36B BGA Pin Description
Symbol
A0, A1
A
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
CKE
W
Clock Input Signal; active high
Clock Enable; active low
I
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ZZ
I
Burst address counter advance enable; active high
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
9th Bit Enable; active low (119-bump BGA only)
I
FT
I
LBO
PE
I
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
TMS
TDI
O
I
Scan Test Data Out
Scan Test Clock
TDO
TCK
MCH
DNU
—
—
I
Must Connect High
Do Not Use
V
Core power supply
I/O and Core Ground
Output driver power supply
DD
V
I
SS
V
I
DDQ
Rev: 1.03 3/2005
6/33
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GSI [ GSI TECHNOLOGY ]
