GS88018/32/36AT-250/225/200/166/150/133
Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tH
tS
tKH
tKC
tS tH
ADSP is blocked by E inactive
ADSC initiated read
ADSP
ADSC
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS
tS
tH
GW
tH
BW
tH
tS
WR1
BWA–BWD
tS
tS
tS
tH
tH
tH
E1 masks ADSP
E1
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2Bb
Q2c
DQA–DQD
Q2D
Rev: 1.02 9/2002
21/26
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.