GS88018/32/36AT-250/225/200/166/150/133
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
CK
tKL
tKH
tH
tH
tS
tKC
ADSP is blocked by E inactive
ADSP
ADSC
tS
ADSC initiated read
tS
tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
A0–An
GW
tS
tS
tH
tH
BW
BWA–BWD
E1
tH
tH
tH
tS
E1 masks ADSP
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOE
G
tOHZ
tKQX
tKQX
Q2D
Q3A
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1A
Q2A
Q2B
Q2c
tHZ
tKQ
Rev: 1.02 9/2002
20/26
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.