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GS8162Z18B-225 参数 Datasheet PDF下载

GS8162Z18B-225图片预览
型号: GS8162Z18B-225
PDF下载: 下载PDF文件 查看货源
内容描述: 18MB流水线和流量通过同步NBT SRAM [18Mb Pipelined and Flow Through Synchronous NBT SRAM]
分类和应用: 静态存储器
文件页数/大小: 38 页 / 1200 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)  
Burst Cycles  
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from  
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address  
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when  
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write  
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into  
Load mode.  
Burst Order  
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been  
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst  
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables  
below for details.  
FLXDrive™  
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive  
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.  
Mode Pin Functions  
Mode Name  
Pin Name  
State  
Function  
Linear Burst  
Interleaved Burst  
Flow Through  
Pipeline  
L
Burst Order Control  
LBO  
H
L
Output Register Control  
Power Down Control  
FT  
ZZ  
ZQ  
H or NC  
L or NC  
H
Active  
Standby, I = I  
DD SB  
L
High Drive (Low Impedance)  
Low Drive (High Impedance)  
FLXDrive Output Impedance Control  
H or NC  
Note:  
There is a are pull-up devicesonthe ZQ and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and  
the chip will operate in the default states as specified in the above tables.  
Rev: 2.21 11/2004  
14/38  
© 1999, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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