GS72108TP/J
TSOP-II 256K x 8-Pin Configuration
NC
NC
A4
1
44
NC
NC
NC
A5
2
43
42
3
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
4
A3
5
A2
A6
6
A1
A7
7
A0
A8
8
CE
OE
DQ8
DQ7
VSS
VDD
DQ6
DQ5
A9
9
DQ1
DQ2
VDD
VSS
DQ3
DQ4
WE
A17
A16
10
11
12
13
14
15
16
17
18
44-pin
400 mil TSOP II
A10
A11
A12
NC
NC
A15
A14
19
20
21
22
A13
NC
NC
24
23
NC
NC
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A17
CE
WE
OE
I/O Buffer
Control
DQ8
DQ1
Rev: 1.08 7/2002
2/12
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
