GS72116ATP/J/T/U
7, 8, 10, 12 ns
SOJ, TSOP, FP-BGA, TQFP
Commercial Temp
Industrial Temp
128K x 16
2Mb Asynchronous SRAM
3.3 V V
DD
Center V and V
DD
SS
Features
Pin Descriptions
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
Symbol
A0–A16
DQ1–DQ16
CE
Description
Address input
Data input/output
Chip enable input
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
Lower byte enable input
(DQ1 to DQ8)
LB
J:
400 mil, 44-pin SOJ package
Upper byte enable input
(DQ9 to DQ16)
UB
GJ: RoHS-compliant 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
WE
OE
Write enable input
Output enable input
+3.3 V power supply
T: 10 mm x 10 mm, 44-pin TQFP
V
DD
GT: RoHS-compliant 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
Array package
V
Ground
SS
NC
No connect
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
SOJ 128K x 16-Pin Configuration
A4
A3
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A6
2
A2
A7
3
A1
OE
4
Top view
A0
UB
5
CE
LB
6
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
7
8
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
SOJ
VSS
DQ5
DQ6
DQ7
DQ8
WE
16
17
18
19
20
21
22
A15
A14
A13
A12
A16
A8
A9
A10
A11
NC
Package J
Rev: 1.09 10/2007
1/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.