GS72116ATP/J/T/U
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
tAB
UB, LB
OE
tBHZ
tOHZ
tBLZ
tOE
tOLZ
Data valid
Data Out
High impedance
Write Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
8
Max
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
12
8
Max
—
—
—
—
—
—
—
—
—
—
—
Write cycle time
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
tWC
tAW
tCW
tBW
tDW
tDH
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5.5
5.5
5.5
4
5
7
8
5
7
8
3.5
0
5
6
Data hold time
0
0
0
Write pulse width
tWP
tAS
5
5.5
0
7
8
Address set up time
0
0
0
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
0
0
0
0
*
3
3
3
3
tWLZ
tWHZ
*
Write to output in High Z
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.09 10/2007
8/18
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
