GS71116TP/J/U
Read Cycle 2: WE = V
IH
tRC
Address
tAA
CE
tAC
tLZ
UB, LB
OE
tBLZ
tOE
Data Out
tOLZ
High impedance
tAB
tBHZ
tOHZ
Data valid
tHZ
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
Data hold time
Write pulse width
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
Write to output in High Z
* These parameters are sampled and are not 100% tested
Symbol
tWC
tAW
tCW
tBW
tDW
tDH
tWP
tAS
tWR
tWR1
tWLZ
*
tWHZ
*
-10
Min
10
7
7
7
5
0
7
0
0
0
3
---
-12
Max
---
---
---
---
---
---
---
---
---
---
---
4
-15
Max
---
---
---
---
---
---
---
---
---
---
---
5
Min
12
8
8
8
6
0
8
0
0
0
3
---
Min
15
10
10
10
7
0
10
0
0
0
3
---
Max
---
---
---
---
---
---
---
---
---
---
---
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev: 1.06 6/2000
8/15
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
