GS4576C09/18/36L
Configuration Tables
The relationship between cycle time and read/write latency is selected by the user. The configuration table below lists valid
configurations available via Mode Register bits M0, M1, and M2 and the clock frequencies supported for each setting. Write
Latency is equal to the Read Latency plus one in each configuration to reduce bus conflicts.
Cycle Time and Read/Write Latency Configuration Table
Configuration
Parameter
Units
2
2, 3
2
3
5
1
4
tRC
4
6
8
3
3
4
5
tCK
tCK
tCK
MHz
tRL
tWL
4
5
6
7
8
9
5
6
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
Notes:
1. tRC < 20 ns in any configuration is only available with –18 and –24 speed grades.
2. BL= 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum
tRC is 4 cycles.
Rev: 1.04 11/2013
18/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
