GS4576C09/18/36L
Mode Register Set
Mode Register Set controls the operating modes of the memory, including configuration, burst length, test mode, and I/O options.
During an MRS command, the address inputs A0–A17 are sampled and stored in the Mode Register. Except during initialization to
force internal reset, after a valid MRS command, tMRSC must be met before any command except NOP can be issued to the
LLDRAM II. All banks must be idle and no bursts may be in progress when an MRS command is loaded.
Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to
invalidate all stored data.
Mode Register Set
CK
CK
CS
WE
REF
Addr
CODE
BA(2:0)
Rev: 1.04 11/2013
16/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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