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GS1284Z18GB-200I 参数 Datasheet PDF下载

GS1284Z18GB-200I图片预览
型号: GS1284Z18GB-200I
PDF下载: 下载PDF文件 查看货源
内容描述: [SRAM]
分类和应用: 静态存储器
文件页数/大小: 29 页 / 644 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS81284Z18/36B-250/200/167  
Burst Counter Sequences  
Linear Burst Sequence  
Interleaved Burst Sequence  
A[1:0] A[1:0] A[1:0] A[1:0]  
A[1:0] A[1:0] A[1:0] A[1:0]  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Note:  
Note:  
The burst counter wraps to initial state on the 5th clock.  
The burst counter wraps to initial state on the 5th clock.  
BPR 1999.05.18  
Sleep Mode  
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,  
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to  
low, the SRAM operates normally after 2 cycles of wake up time.  
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of  
SB  
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become  
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.  
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending  
SB  
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated  
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands  
may be applied while the SRAM is recovering from Sleep mode.  
Sleep Mode Timing Diagram  
tKH  
tKC  
tKL  
CK  
ZZ  
tZZR  
tZZS  
tZZH  
Designing for Compatibility  
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not  
all vendors offer this option, however most mark the pin V or V on pipelined parts and V on flow through parts. GSI NBT  
DD  
DDQ  
SS  
SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal  
pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode  
part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device,  
the pin will need to be pulled low for correct operation.  
Rev: 1.02 7/2010  
11/29  
© 2007, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.