欢迎访问ic37.com |
会员登录 免费注册
发布采购

G2995P1T 参数 Datasheet PDF下载

G2995P1T图片预览
型号: G2995P1T
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit, 1 Func, PDSO8, MS-012, SOP-8]
分类和应用: 光电二极管接口集成电路
文件页数/大小: 12 页 / 362 K
品牌: GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
 浏览型号G2995P1T的Datasheet PDF文件第4页浏览型号G2995P1T的Datasheet PDF文件第5页浏览型号G2995P1T的Datasheet PDF文件第6页浏览型号G2995P1T的Datasheet PDF文件第7页浏览型号G2995P1T的Datasheet PDF文件第8页浏览型号G2995P1T的Datasheet PDF文件第10页浏览型号G2995P1T的Datasheet PDF文件第11页浏览型号G2995P1T的Datasheet PDF文件第12页  
Global Mixed-mode Technology Inc.
Typical Application Circuits
There are several application circuits shown in Figure
2 through 8 to illustrate some of the possible configu-
rations of the G2995. Figure 2~4 are the SSTL-2 ap-
plications. For the majority of applications that imple-
G2995
ment the SSTL-2 termination scheme, it is recom-
mended to connect all the input rails to 2.5V rail, as
seen in Figure 2. This provides an optimal trade-off
between power dissipation and component count.
V
DDQ
=2.5V
V
DD
=2.5V
V
DDQ
V
REF
V
SENSE
V
TT
GND
+
V
REF
=1.25V
C
REF
AV
IN
PV
IN
C
IN
+
V
TT
=1.25V
+
C
OUT
Figure 2. Recommended SSTL-2 Implementation
In Figure 3, the power rails are split. The power rail of
the output stage (PVIN) can be as low as 1.8V, the
power rail of the analog circuit (AVIN) is operated
above 2V. The lower output stage power rail can lower
the internal power dissipation when sourcing from the
device and improve the efficiency, but the disadvan-
tage is the maximum continuous current sourcing from
V
TT
is reduced. This configuration is applied when the
power dissipation and efficiency are concerned.
V
DDQ
=2.5V
V
DDQ
V
REF
V
SENSE
V
TT
GND
+
V
REF
=1.25V
C
REF
AV
IN
=1.8V or 5.5V
PV
IN
=1.8V
C
IN
+
AV
IN
PV
IN
V
TT
=1.25V
+
C
OUT
Figure 3. Lower Power Dissipation SSTL-2 Implementation
In Figure 4, the power rail of the output stage (PVIN) is
connected to 3.3V to increase the maximum continu-
ous current sourcing from V
TT
. AVIN should be always
equal to or larger than PVIN. This configuration can
increase the source capability of this device, but the
power dissipation increases at the same time. It
should be more careful to prevent the junction tem-
perature from exceeding the maximum rating. Be-
cause of this risk, it is not recommended to supply the
output stage power rail (PVIN) with a voltage higher
than a nominal 3.3V rail.
V
DDQ
=2.5V
V
DDQ
V
REF
V
SENSE
V
TT
GND
+
V
REF
=1.25V
C
REF
AV
IN
=3.3V or 5V
PV
IN
=3.3V
C
IN
+
AV
IN
PV
IN
V
TT
=1.25V
+
C
OUT
Figure 4. SSTL-2 Implementation with higher voltage rails
Ver: 1.6
Jul 26, 2004
TEL: 886-3-5788833
http://www.gmt.com.tw
9