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G2995P1T 参数 Datasheet PDF下载

G2995P1T图片预览
型号: G2995P1T
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit, 1 Func, PDSO8, MS-012, SOP-8]
分类和应用: 光电二极管接口集成电路
文件页数/大小: 12 页 / 362 K
品牌: GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
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Global Mixed-mode Technology Inc.  
G2995  
In Figure 5 & 6, they are the application configurations  
of DDR-II SDRAM bus terminations. Figure 5 is the  
typical application scheme of DDR-II SDRAM. With the  
separate VDDQ pin and an internal resistor divider, it  
is possible to use the G2995 in applications utilizing  
DDR-II memory. Figure 6 is used to increase the driv-  
ing capability. The risk is the same as figure 4.  
VREF  
VREF=0.9V  
VDDQ  
VDDQ=1.8V  
+
+
CREF  
VSENSE  
VTT  
AVIN=1.8V or 5.5V  
PVIN=1.8V  
AVIN  
PVIN  
VTT=0.9V  
COUT  
+
GND  
CIN  
Figure 5. Recommended DDR-II Termination  
VREF  
VREF=0.9V  
CREF  
VDDQ  
VDDQ=1.8V  
+
VSENSE  
VTT  
AVIN=3.3V or 5.5V  
PVIN=3.3V  
AVIN  
PVIN  
VTT=0.9V  
COUT  
+
+
GND  
CIN  
Figure 6. DDR-II Termination with higher voltage rails  
Figure 7 & 8 are used to scale the VTT to the wanted  
value when the standard voltages of SSTL-2 do not  
meet the requirements. Using R1 & R2, Figure 7 can  
shift VTT up to VDDQ/2 * (1+R1/R2) and figure 8 can  
shift VTT down to VDDQ/2 * (1-R1/R2).  
VDDQ  
VDD  
VDDQ  
AVIN  
PVIN  
VTT  
VTT  
COUT  
R1  
R2  
+
VSENSE  
+
GND  
CIN  
Figure 7. Increasing VTT by Level Shifting  
R2  
VDDQ  
VDD  
VDDQ  
AVIN  
PVIN  
VSENSE  
R1  
VTT  
COUT  
VTT  
+
+
GND  
CIN  
Figure 8. Decreasing VTT by Level Shifting  
TEL: 886-3-5788833  
http://www.gmt.com.tw  
Ver: 1.6  
Jul 26, 2004  
10