Global Mixed-mode Technology Inc.
G1426
Application Information
Bridged-Tied Load Mode Operation
Optimizing DEPOP Operation
G1426 has two linear amplifiers to drive both ends of
the speaker load in Bridged-Tied Load (BTL) mode
operation. Figure 1 shows the BTL configuration. The
differential driving to the speaker load means that
when one side is slewing up, the other side is slewing
down, and vice versa. This configuration in effect will
double the voltage swing on the load as compared to a
ground reference load. In BTL mode, the peak-to-peak
voltage VO(PP) on the load will be two times than a
ground reference configuration. The voltage on the
load is doubled, this will also yield 4 times output
power on the load at the same power supply rail and
loading. Another benefit of using differential driving
configuration is that BTL operation cancels the dc off-
sets, which eliminates the dc coupling capacitor that is
needed to cancelled dc offsets in the ground reference
configuration. Low-frequency performance is then lim-
ited only by the input network and speaker responses.
Cost and PCB space can be minimized by eliminating
the dc coupling capacitors.
Circuitry has been implemented in G1426 to mini-
mize the amount of popping heard at power-up and
when coming out of shutdown mode. Popping oc-
curs whenever a voltage step is applied to the
speaker and making the differential voltage gener-
ated at the two ends of the speaker. To avoid the
popping heard, the bypass capacitor should be
chosen promptly, 1/(C x100k ) ≦ 1/(C *(R +R )).
Ω
B
I
I
F
Where 100k
Ω
is the output impedance of the
mid-rail generator, CB is the mid-rail bypass capaci-
tor, CI is the input coupling capacitor, RI is the input
impedance, RF is the gain setting impedance which
is on the feedback path. CB is the most important
capacitor. Besides it is used to reduce the popping,
CB can also determine the rate at which the amplifier
starts up during startup or recovery from shutdown
mode.
De-popping circuitry of G1426 is shown on Figure 2.
The PNP transistor limits the voltage drop across
the 225kΩ by slewing the internal node slowly when
power is applied. At start-up, the voltage at
BYPASS capacitor is 0. The PNP is ON to pull the
mid-point of the bias circuit down. So the capacitor
sees a lower effective voltage, and thus the charg-
ing is slower. This appears as a linear ramp (while
the PNP transistor is conducting), followed by the
expected exponential ramp of an R-C circuit.
VDD
Vo(PP)
RL
2xVo(PP)
-Vo(PP)
VDD
VDD
Figure 1
Vo(PP)+VDD/2
RL
Vo(PP)
SHUTDOWN Mode Operations
G1426 implements the shutdown mode operations
to reduce supply current, IDD, to the absolute mini-
mum level during nonuse periods for battery-power
conservation. When the shutdown pin (pin 1) is
pulled high, all linear amplifiers will be deactivated
to mute the amplifier outputs. And G1426 enters an
extra low current consumption state, IDD is smaller
than 2µA. Shutdown pin should never be left un-
connected, this floating condition will cause the am-
plifier operations unpredictable.
VDD/2
VDD/2
Figure 2
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.0
Dec 04, 2003
11
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
