Table 1-1: Pin Descriptions (Continued)
Pin Number
19
Name
SDOUT_TDO
Timing
Synchronous
with
SCLK_TCK
Type
Output
Description
CONTROL SIGNAL
INPUT
Signal
levels are LVCMOS / LVTTL
compatible.
Serial
Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO
operates as the host interface serial output,
SDOUT,
used to read status and
configuration
information from the
internal registers of the
device.
JTAG
Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO
operates as the
JTAG
test
data
output, TDO.
20
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL
INPUT
Signal
levels are LVCMOS / LVTTL
compatible.
Serial
Data Input / Test Data Input
Host Mode (JTAG/HOST = LOW):
SDIN_TDI
operates as the host interface serial input,
SDIN,
used to
write address and
configuration
information to the internal
registers of the
device.
JTAG
Test Mode (JTAG/HOST = HIGH):
SDIN_TDI
operates as the
JTAG
test
data
input, TDI.
21, 29, 43
IO_VDD
Non
Synchronous
Input
Power
Power supply for
digital
I/O.
For a 3.3V tolerant I/O,
connect
pins to either +1.8V DC or +3.3V
DC.
For a 5V tolerant I/O,
connect
pins to a +3.3V DC.
NOTE: For power sequencing requirements please see
22
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL
OUTPUT.
Signal
levels are LVCMOS / LVTTL
compatible.
The DATA_ERROR signal will
be
LOW when an error within the
received
data
stream has
been detected by
the
device.
This pin is an
inverted logical ‘OR’ing of all
detectable
errors listed in the internal
ERROR_STATUS register.
Once an error is
detected,
DATA_ERROR will remain LOW until the
start of the next video frame / field, or until the ERROR_STATUS
register is read via the host interface.
The DATA_ERROR signal will
be
HIGH when the received
data
stream has
been detected
without error.
NOTE: It is possible to program which error
conditions
are
monitored
by
the
device by
setting appropriate
bits
in the
ERROR_MASK register HIGH. All error
conditions
are
detected by
default.
GS9090A GenLINX® III 270Mb/s Deserializer
Data Sheet
34714 - 7
May 2010
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