Table 1-1: Pin Descriptions (Continued)
Pin Number Name
Timing
Type
Description
13
JTAG/HOST
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured as GSPI pins for normal host interface operation.
14
RESET
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default setting
or to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all functional blocks will be set to default
conditions and all output signals become high impedance with the
exception of the STAT pins and the DATA_ERROR pin which will
maintain the last state they were in for the duration that RESET is
asserted.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all functional blocks will be set to default and
the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence
resumes.
NOTE: See Device Power Up on page 65 for power on reset
requirements.
15, 45
16
CORE_VDD
CS_TMS
Non
Synchronous
Input
Power supply for digital logic blocks. Connect to +1.8V DC.
Power
NOTE: For power sequencing requirements please see Device
Power Up on page 65.
Synchronous
with
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
SCLK_TCK
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW):
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH):
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
17
SCLK_TCK
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Clock / Test Clock. All JTAG / Host Interface address and
data are shifted into/out of the device synchronously with this
clock.
Host Mode (JTAG/HOST = LOW):
SCLK_TCK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCK operates as the JTAG test clock, TCK.
18, 48
CORE_GND
Non
Input
Ground connection for digital logic blocks. Connect to GND.
Synchronous
Power
GS9090A GenLINX® III 270Mb/s Deserializer
Data Sheet
7 of 73
34714 - 7
May 2010
GENNUM [ GENNUM CORPORATION ]
