5.1 Lock Time
TABLE 3: Data Rate Select in Manual Mode
The lock time of the GS9035A depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data to the
GS9035A is changed from one source to another source
which is at a different data rate.
AUTO/MAN = 0 (Manual Mode)
ƒH, ƒL = VCO center frequency as per Figure 8
DIVIDER
MODULI
SMPTE
SS[2:0]
PLL CLOCK
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
4
2
2
1
1
8
8
-
ƒH/4
ƒL/2
ƒH/2
ƒL
When input data to the GS9035A is removed, the GS9035A
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9035A begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9035A locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the table below:
ƒH
ƒL/8
ƒH/8
-
TABLE 4: Lock Time Relative to Switching Time
4
4
2
2
1
1
8
-
ƒH/4
ƒH/4
ƒH/2
ƒH/2
ƒH
SWITCHING TIME
<0.5µs
LOCK TIME
10µs
0.5µs - 10ms
> 10ms
2tsys
2Tcycle + 2tsys
ƒH
In asynchronous switching applications (including power
up) the lock time is determined by the frequency acquisition
circuit as described in section 2, Frequency Acquisition. In
manual mode, the frequency acquisition circuit may have to
sweep over an entire cycle (depending on initial conditions)
ƒH/8
-
to acquire lock resulting in a maximum lock time of 2Tcycle
2tsys. In auto tune mode, the maximum lock time is 6Tcycle
+
+
5. LOCKING
The GS9035A indicates lock when three conditions are
satisfied:
2tsys since the frequency acquisition circuit may have to
cycle through 5 possible counter states (depending on
initial conditions) to acquire lock. The nominal value of Tcycle
for the GS9035A operating in a typical SMPTE 259M
application is approximately 1.3ms.
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
The GS9035A has a dedicated LOCK output (pin 3)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
3. The system is not locked to a harmonic.
The GS9035A defines the presence of input data when at
least one data transition occurs every 1µs.
The GS9035A assumes that it is NOT locked to a harmonic
if the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every tsys/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. (In an harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.)
5.2 DVB-ASI
Design Note: For DVB-ASI applications having significant
instances of few bit transitions or when only K28.5 idle bits
are transmitted, the wide-band PLL in the GS9035A may
lock at 243MHz being the first 27MHz sideband below
270MHz. In this case, when normal bit density signals are
transmitted, the PLL will correctly lock onto the proper
270MHz carrier.
9 of 14
GENNUM CORPORATION
522 - 41 - 08
GENNUM [ GENNUM CORPORATION ]
