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GS9035ACPJE3 参数 Datasheet PDF下载

GS9035ACPJE3图片预览
型号: GS9035ACPJE3
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH Clock Recovery Circuit, PQCC28,]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 14 页 / 239 K
品牌: GENNUM [ GENNUM CORPORATION ]
 浏览型号GS9035ACPJE3的Datasheet PDF文件第1页浏览型号GS9035ACPJE3的Datasheet PDF文件第2页浏览型号GS9035ACPJE3的Datasheet PDF文件第3页浏览型号GS9035ACPJE3的Datasheet PDF文件第4页浏览型号GS9035ACPJE3的Datasheet PDF文件第6页浏览型号GS9035ACPJE3的Datasheet PDF文件第7页浏览型号GS9035ACPJE3的Datasheet PDF文件第8页浏览型号GS9035ACPJE3的Datasheet PDF文件第9页  
PIN DESCRIPTIONS
(continued)
NUMBER
16
17
18
19 - 21
SYMBOL
R
VCO
CBG
V
CC2
SS[2:0]
TYPE
I
I
I
I/O
Frequency setting resistor.
Internal bandgap voltage filter capacitor.
Most positive power supply connection.
DESCRIPTION
GS9035A
Data rate indication (Auto mode) or data rate select (Manual mode). TTL/CMOS compatible I/O. In
auto mode these pins can be left unconnected.
Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω
pullup resistors.
Serial data output. SDO/SDO are differential current mode outputs and require external 75Ω pullup
resistors.
Most positive power supply connection.
Clock enable. When HIGH, the serial clock outputs are enabled.
22, 23
SCO/SCO
O
24, 25
SDO/SDO
O
26
28
V
CC3
CLK_EN
I
I
TYPICAL PERFORMANCE CURVES
(V
S
= 5V, T
A
= 25°C unless otherwise shown.)
Fig. 2 Intrinsic Jitter (2 -1 Pattern) 30Mb/s
23
Fig. 4 Intrinsic Jitter (2 -1 Pattern) 270Mb/s
23
Fig. 3 Intrinsic Jitter (2 -1 Pattern) 143Mb/s
23
Fig. 5 Intrinsic Jitter (2
23
-1 Pattern) 540Mb/s
5 of 14
GENNUM CORPORATION
522 - 41 - 08