DETAILED DESCRIPTION
1.2 Parallel Clock Inputs
The GS9021 EDH coprocessor consists of five major
blocks:
PIN
LOGIC OPR
HOST BIT
1. Data Input/Output Block (with automatic standard
detect)
PCLKIN
2. Flywheel Block
3. EDH Block
The PCLKIN pin is the input used to clock the video data
into the GS9021, and serves as the reference to which all
synchronous inputs and outputs are timed. The following
table shows which pins are synchronous with PCLKIN and
which are not. Timing for synchronous I/O is found in
Figures 1 and 2.
4. Data Processing Block
5. Host Interface (HOSTIF) Block
The following convention is used to differentiate device pins
from HOST interface table bits.
SYNCHRONOUS
FL[4:0]
ASYNCHRONOUS
P[7:5]
PIN
LOGIC OPR
HOSTIF
XX
YY
S[1:0]
SCL/P4
FIFO_RESET
DOUT[9:0]
F[2:0]
INTERRUPT
SDA/P3
LOGIC OPR (logic operator) gives the combinational
relationship (if one exists), between pins which also have a
corresponding HOST bit. This operator governs the signal
the GS9021 receives. The following is the list of possible
logic operators and their meaning.
A[2:0]/P[2:0]
R/W
V
H
A/D
LOGIC OPR
MEANING
XX AND YY
ANC_DATA
BLANK_EN
F_R/W
CS
AND
OR
>
FLAG_MAP
RESET
XX OR YY
XX takes precedence over YY
YY takes precedence over XX
NO_EDH
STD[3:0]
TRS_ERROR
DIN[9:0]
CRC_MODE
VBLANKS/L
HOSTIF_MODE
FIFOE/S
<
1. DATA INPUT/OUTPUT BLOCK
1.1 Parallel Digital Video Data Inputs
FLYWDIS
BYPASS_EDH
SDO_MODE
ANC_CHKSM
CLIP_TRS
PIN
LOGIC OPR
HOST BIT
DOUT[9:0]
Parallel digital video data is supplied to the GS9021 chip
via the DIN[9:0] input pins. The data is clocked into the
GS9021 by the rising edge of PCLKIN.
Eight input signal standards are supported: Composite,
4:2:2 Component with 13.5MHz Y sampling, 4:2:2 16 x 9
wide screen with 18 MHz Y sampling, and 4:4:4:4
Component Single Link with 13.5MHz Y sampling, all in
both NTSC and PAL formats (See Table 1). Both 8 and 10
bit inputs are supported. However, when using 8 bit data,
the 2 LSBs of the input must be tied to GND.
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