FIELD 0
FIELD 1
FIELD 2
E
D
H
F1
E
D
H
F0
DIN[9:0]
t
0
E
D
H
F1
E
D
H
F0
DOUT[9:0]
2 LINES
VALID TIME TO READ/WRITE
EDH INFORMATION TO/FROM GS9021
Fig. 9 Host Interface Read/Write Timing
t
= 25µs
MAX
INTERNAL
POWER on
RESET CELL
INTERNAL
RESET
SIGNAL
RESET
PIN
t
RESET
Fig. 10a Reset Circuitry
~1.4 mS
V
DD
V
DD
5V
2k
0V
5V
t
RESET
RESET
Manual
Reset
Switch
20k
1uF
(Optional)
0V
t
Fig. 10b Acceptable external reset circuit when a master reset is not available
24
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