2.
DETAILED DESCRIPTION
When “VSEL” is LOW, the video input standard is selected
by the VM[2:0] and TRS input pins. When “VSEL” is HIGH,
the video input standard is selected by the “VMOD[2:0]”
and “D2_TRS” bits in Host Interface Register #0h. The
supported video input standards are listed in Table 1.
After the user has specified the video input standard via the
VM[2:0] and TRS pins or by setting Host Interface Register
#0h, the GS9023A performs video standard detection to
verify that the input video stream corresponds to the
selected standard. The LOCK output pin and the “LOCK”
bit of Host Interface Register #0h are then set HIGH if at
least one of the audio channel enable bits “CHACT(4-1)” of
Host Interface Register #1h is HIGH and the start of a video
frame is detected.
NOTE: The user must ensure that the video input format
correctly corresponds to the video format being provided to
the GS9023A. For 8-bit video operation, the "8BIT_SEL" bit
of the Host Interface Register #2h must be set HIGH.
The GS9023A has two main modes of operation: Multiplex
Mode and Demultiplex Mode. In Multiplex Mode, which is
selected by setting the DEMUX/MUX input pin LOW, digital
audio is embedded into a digital video stream. In
Demultiplex Mode, which is selected by setting the DEMUX/
MUX input pin HIGH, digital audio is extracted from a digital
video stream. Table 14 and Table 15 contain Host Interface
Register descriptions for the Multiplex and Demultiplex
Modes respectively.
2.1
MULTIPLEX MODE
GS9023A
2.1.1 Video Clock Input
A master video clock must be supplied to the PCLK pin
corresponding to the selected video standard. The
supported video input standards and corresponding clock
frequencies are listed in Table 1.
2.1.2 Video Data Input
The video data DIN[9:0] is clocked into the GS9023A on the
rising edge of PCLK. The video clock frequency must
correspond to the video input standard selected. This is
done via the “VSEL” bit of Host Interface Register #0h.
TABLE 1 VIDEO INPUT FORMATS
SERIAL DIGITAL
DATA RATE
(MBPS)
143
143
270
-
360
-
540
-
177
177
270
-
360
-
540
540
PCLK
FREQUENCY
(MHZ)
14.3
14.3
27.0
-
36.0
-
54.0
-
17.7
17.7
27.0
-
36.0
-
54.0
54.0
VIDEO STANDARD
525/D2 (SMPTE259M)
525/D2 (SMPTE244M)
525/D1
Reserved
525/16:9
Reserved
525/4:4:4:4 (System #1)
Reserved
625/D2 (with TRS)
625/D2 (without TRS)
625/D1
Reserved
625/16:9
Reserved
625/4:4:4:4 (System #2)
625/4:2:2P (System #4)
VM[2] OR
“VMOD[2]”
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VM[1] OR
“VMOD[1]”
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VM[0] OR
“VMOD[0]”
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TRS OR
“D2_TRS”
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GENNUM CORPORATION
8 of 37
19795 - 6
GENNUM [ GENNUM CORPORATION ]
