GS9022A PIN DESCRIPTIONS
NOT RECOMMENDED FOR NEW DESIGNS SEE GS9032
PIN NO.
1
2
3-12
13
14
15
16
17
18
19
20
21
22, 23
24
25
26
27
28
SYMBOL
V
CC
V
CC
PD0-PD9
PCKIN
LOCK DET
V
EE
V
CC
LF
V
EE
R
VCO
V
CC
V
EE
SDO, SDO
V
CCSD
SYNC DET
DISABLE
C
OSC
V
EE
C
REG
TYPE
DESCRIPTION
Power Supply: Most positive power supply connection for the PLL and Scrambler.
Power Supply: Most positive power supply connection for the parallel data inputs and P/S
converter.
I
I
O
TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB.
TTL level input of the parallel clock.
TTL level output which goes high when the internal PLL is locked.
Power Supply: Most negative power supply connection.
Power Supply: Most positive power supply connection for the PLL and Scrambler.
I
Connection for the R-C loop filter components.
Power Supply: Most negative power supply connection.
I
VCO frequency setting resistor. A 1% resistor is required.
Power Supply: Most positive power supply connection for the PLL and Scrambler.
Power Supply: Most negative power supply connection.
I
75
Ω
cable driver outputs (true and inverse).
Power Supply: Most positive power supply for cable driver outputs.
I
I
I
I
TTL level input that disables the internal sync detector when high. This allows the GS9022 to
serialize 8 or 10 bit non-SMPTE standard parallel data.
Toggles VCO between ƒ and ƒ/2.
Power Supply: Most negative power supply connection.
Compensation capacitor for internal voltage regulator that requires decoupling with a
0.1 µF capacitor located as close as possible to the pin in series with an 820
Ω
Resistor.
18325 - 01
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GENNUM [ GENNUM CORPORATION ]
