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GS9022A Digital Video Serializer - Detailed Device Description
The GS9022A Serializer is a bipolar integrated circuit used to
convert parallel data into a serial format according to the
SMPTE 259M standard. The device encodes both eight and
ten bit TTL-compatible parallel signals producing serial data
rates up to 400 Mb/s. It operates from a single five volt supply
and is packaged in a 28 pin PLCC.
Functional blocks within the device include the input latches,
sync detector, parallel to serial converter, scrambler, NRZ to
NRZI converter, internal cable driver, PLL for 10 x parallel
clock multiplication and lock detect.
The parallel data (PD0-PD9) and parallel clock (PCKIN) are
applied via pins 3 through 13 respectively.
Sync Detector
The Sync Detector looks for the reserved words 000-003 and
3FC-3FF, in ten bit hexadecimal, or 00 and FF in eight bit
hexadecimal, used in the TRS-ID sync word. When the
occurrence of either all zeros or all ones at inputs PD2-PD9 is
detected, the lower two bits PD0 and PD1 are forced to zeros
or ones, respectively. This makes the system compatible with
eight or ten bit data. For non - SMPTE standard parallel data,
a logic input, Sync Detect Disable (25) is available to disable
this feature.
Scrambler
The Scrambler is a linear feedback shift register used to
pseudo-randomize the incoming serial data according to the
fixed polynomial (X
9
+X
4
+1). This minimizes the DC component
in the output serial data stream. The NRZ to NRZI converter
uses another polynomial (X+1) to convert a long sequence of
ones to a series of transitions, minimizing polarity effects.
Phase Locked Loop
The PLL performs parallel clock multiplication and provides
the timing signal for the serializer. It is composed of
a phase/frequency detector, charge pump, VCO
,
a
divide-by-ten counter, and a divide by two counter.
The phase/frequency detector allows a wider capture range
and faster lock time than that which can be achieved with a
phase discriminator alone. The discrimination of frequency
also eliminates harmonic locking. With this type of discriminator,
the PLL can be over-damped for good stability without
sacrificing lock time.
The charge pump delivers a 'charge packet' to the loop filter
which is proportional to the system phase error. Internal
voltage clamps are used to constrain the loop filter voltage
between approximately 1.8 and 3.4 volts.
The VCO, constructed from a current-controlled multivibrator,
features operation in excess of 400 Mb/s and a wide pull
range (
≈
± 40% of centre frequency).
VCO Centre Frequency Selection
The wide VCO pull range allows the PLL to compensate for
variations in device processing, temperature variations and
changes in power supply voltage, without external adjustment.
A single external resistor is used to set the VCO current for all
standards.
The COSC pin is used to configure the VCO of the GS9022A
in one of three modes, as shown below:
C
OSC
0.1µF to GND
10k Resistor to VCC
10k Resistor to GND
Mode
Auto Standard
ƒ/2 ON
ƒ/2 OFF
NOT RECOMMENDED FOR NEW DESIGNS SEE GS9032
In auto standard mode, the capacitor sets the sweep rate at
which the VCO toggles between ƒ and ƒ/2.
The ƒ/2 ON and ƒ/2 OFF modes are used to configure the
GS9022A VCO for single standard operation.
The lock detect circuit disables the serial data output when the
loop is not locked. The Lock Detect output is available from pin
14 and is HIGH when the loop is locked.
The true and complement serial data, SDO and SDO are
available from pins 22 and 23. These outputs will drive
two 75
Ω
co-axial cables with SMPTE level serial digital
video signals.
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GENNUM [ GENNUM CORPORATION ]
