Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
DesignoftheGS90005A/15A”.ArecommendedPCBlayoutcanbefoundintheGennumApplicationNote“EB9010BDeserializer
Evaluation Board”
The use of a star grounding technique is required for the loop filter components of the GS9005A/15A.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and
theGS9000BorGS9000S. Thesedifferentialtracesmustnotpassoveranygroundplanediscontinuities. Aslotantennaisformed
when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
DVCC
+5V
VCC
+5V
SWF
+
+
100
10µ
10µ
3.3k
100
100
DGND
DGND
GND
VCC
0.1µ
SYNC WARNING FLAG
HSYNC OUTPUT
DGND
DGND
390
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
4
3
2
1
28 27 26
4
3
2
1
28 27 26
390
100
100
25
24
23
22
21
20
19
100
100
100
100
5
6
PD7
PD6
25
24
23
22
21
20
19
SDI
SDI
SCI
SCI
SS1
SS0
SST
SDO
5
6
SERIAL
DIGITAL
INPUT
VCC
DDI
(3)
SDO
SCO
SCO
SS1
SS0
CD
PD5
PD4
PD3
PD2
PD1
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
DDI
7
100
100
390
GS9000B
7
8
VCC1
VEE1
VEE1
ƒ/2
8
GS9015A
or GS9000S
100
100
0.1µ
VCC
9
9
10
11
10
11
390
100
VEE3
DVCC
12 13 14 15 16 17
18
DVCC
12 13 14 15 16 17 18
VCC
5.6p
0.1µ
DGND
0.1µ
910
100
100
0.1µ
(1)
10n
DGND
DVCC
1.2k
VCC
1.2k
(2)
0.1µ
68k
50k
22n
VCC
120
DGND
STAR
ROUTED
GS9010A
(1)
+
0.1µ
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
6.8µ
STDT
P/N
OUT
IN-
6.8µ
V
CC
CD
+
HSYNC
GND
COMP
LF
3.3n
VCC
OSC
ƒ/2
STANDARD TRUTH TABLE
DLY
100k
V
VCC
CC
FVCAP
SWF
ƒ/2
0
P/N
0
STANDARD
82n
(1)
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
0.68µ
VCC
0
1
0.1µ
All resistors in ohms,
1
0
180n
all capacitors in microfarads,
SWF
1
1
all inductors in henries unless otherwise stated.
(1) To reduce board space, the two anti-series 6.8 µF capacitors (connected across pins 2 and 3 of
the GS9010A) may be replaced with a 1.0 µF non-polarized capacitor provided that:
(a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
0.33 µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10 nF.
(2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
a maximum of 300 Mbps.
Fig. 17 Typical Application Circuit
12
520 - 99 - 05
GENNUM [ GENNUM CORPORATION ]
