0.1µ
-5V
390
4
3
2
1 28 27 26
-5V
390
100
100
25
24
23
22
21
20
19
DATA
DATA
5
6
SDO
ECL
DATA
INPUTS
DDI
SDO
SCO
SCO
SS1
DDI
100
100
CLOCK
CLOCK
7
VCC1
VEE1
VEE1
ƒ/2
GS9015A
0.1µ
8
9
390
390
SS0
CD
10
11
CARRIER
DETECT
OUTPUT
VEE3
-5V
10k
12 13 14 15 16 17 18
0.1µ
5.6p
10n
910
-5V
÷2
÷1
See Figure 15
STAR
ROUTED
LOOP
VOLTAGE
-5V
-5V
-5V
All resistors in ohms, all capacitors in microfarads unless otherwise stated.
Fig. 14 GS9015A Typical Test Circuit Using -5V Supply
VCO Frequency Setting Resistors
When ƒ/2 (Pin 10) is HIGH, two of the RVCO pins are assigned
to data rates below 200 Mb/s and two are assigned to data
rates over 200 Mb/s. The selection is dependent upon the
level of STANDARD SELECT BIT, SS1 (pin 21). When SS1
is LOW, RVCO0 andRVCO1(pins13and14)areusedforthe
higher data rates. When SS1 is HIGH, the VCO frequency is
now twice the bit rate and its frequency is set by RVCO2 and
RVCO3 (pins 15 and 17).
There are two modes of VCO operation available in the
GS9015A depending on the state of the ÷2 block. The ÷2
blockisenabledaccordingto:÷2ENABLE=ƒ/2•SS1. When
the ƒ/2 ENABLE (pin 10) is LOW, any of the four VCO
frequency setting resistors, RVCO0 through RVCO3, (pins
13, 14, 15 and 17) maybeusedforanydata rate from100
Mb/s to 400 Mb/s. For example, for 143 Mb/s data
rate, the value of the total RVCO resistance is approximately
6k8 and for 270 Mb/s operation, the value is
approximately 3k5. The 5k potentiometers will then tune
the desired data rate near their mid-points.
For 143 Mb/s and 270 Mb/s operation, (the VCO is at
286 MHz and 270 MHz respectively) the total resistance
required is approximately the same for both data rates. This
also applies for 177 Mb/s and 360 Mb/s operation (the VCO
is tuned to 354 MHz and 360 MHz respectively). This means
that one potentiometer may be used for each frequency pair
with only a small variation of the fixed resistor value. This
halves the number of adjustments required.
Jitter performance at the lower data rates (143, 177 Mb/s) is
improvedbyoperatingtheVCOattwicethenormalfrequency.
This is accomplished by enabling the divide by two block in
the PLL section of the GS9015A.
10
520 - 99 - 05
GENNUM [ GENNUM CORPORATION ]
