SSI
V
CC
+5V
10µ
+
DV
CC
+5V
10µ
+
V
CC
GND
DGND
ECL
DATA
INPUT
5
V
CC
6 DDI
DDI
0µ1
7
V
CC2
47p
8 SDI
9 SDI
10 ƒ/2
47p
11 V
EE3
5p6
113
10n
(2)
10µ
+
0µ1
V
CC
0µ1
V
CC
SWF
100
3k3
DGND
100
100
INPUT SELECTION
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
0µ1
0µ1
DGND
V
SS
SWF
V
SS
HSYNC
PD9
PD8
V
SS
DGND
4
3 2
1 28 27 26
PD7
PD6
PD5
PD4
PD3
PD2
PD1
V
DD
4
3 2
1 28 27 26
25
SDO 24
SDO 23
SCO 22
SCO 21
SS1 20
SS0
19
CD
390
390
100
100
100
100
V
CC
390
390
5
6
7
8
9
10
11
GS9000C
V
CC
1
V
EE1
AGC
A/D
SSI
V
EE2
V
CC4
25
24
23
22
21
20
19
DV
CC
0µ1
INPUT
75
GS9005A
LOOP
R
VCO0
R
VCO1
R
VCO2
EYE
OUT
R
VCO3
V
CC3
PCLK
V
DD
V
DD
SCE
SWC
75
22n(1)
12 13 14 15 16 17 18 V
CC
910
DV
CC
12 13 14 15 16 17
PDO
SDI
SDI
SCI
SCI
SS1
SS0
SSC
GS9000C
100
100
100
100
100
100
100
18
0µ1
DGND
1k2
1k2
0µ1
50k
(3)
100 100
DGND
V
CC
DV
CC
68k
22n
V
CC
STAR
ROUTED
6µ8
+
120
DGND
GS9010A
(2)
6µ8 +
V
CC
16
STDT
P/N
V
CC
15
OUT
3
CD 14
IN-
4
HSYNC 13
COMP
3n3 5 LF
GND 12
6 ƒ/2
OSC 11
7 V
DLY 10
CC
8 SWF
FVCAP 9
2
1
0.1µ
V
CC
100k
82n
0µ68
(2)
STANDARD TRUTH TABLE
ƒ/2
0
0
1
1
P/N
0
1
0
1
STANDARD
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
0µ1
SWF
V
CC
180n
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8µF capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0µF non-polarized capacitor provided that
(a) the 0.68µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
Fig. 11 Application Circuit - Adjustment Free Multi-standard Serial to Parallel Convertor
GS9000C, GS9005A and GS9010A INTERCONNECTIONS
Figure 11 shows an application of the GS9000C in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-system
IC and a GS9005A Serial Digital Receiver. The GS9005A may
be replaced with a GS9015A Reclocker IC if cable equalization
is not required.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the incoming
data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. An
automatic fine tuning (AFT) loop maintains the VCO control
voltage at its centre point through continuous, long term
adjustments of the VCO centre frequency.
During normal operation, the GS9000C Decoder provides
continuous HSYNC pulses which disable the ramp/oscillator
of the GS9010A. This maintains the correct Receiver/
Reclocker VCO frequency. When an interruption to the incoming
data stream is detected by the Receiver/Reclocker, the
Carrier Detect goes LOW and tri-states the AFT loop in order
to maintain the correct VCO frequency for a period of about
2 seconds. This allows the Receiver/Reclocker to rapidly
relock when the signal is re-established.
7
522 - 49 - 01
GENNUM [ GENNUM CORPORATION ]
