GS9000C PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
15
SWC
Input
Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
16
17
PCLK
PD0
Output
Output
Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is
located at the centre of the parallel data window within a given tolerance. See Fig. 7.
Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from
the serial to parallel convertor representing the least significant bit (LSB).
18
V
Power Supply. Most positive power supply connection.
DD
19 - 25
PD1 - PD7 Outputs
Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from
the serial to parallel convertor representing data bit 1 through data bit 7.
26
27
V
Power Supply. Most negative power supply connection.
SS
PD8
Output
Output
Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to
parallel convertor representing data bit 8.
28
PD9
Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial
to parallel convertor representing the most significant bit (MSB).
INPUT / OUTPUT CIRCUITS
V
V
V
DD
DD
DD
V
DD
R
EXT
SSC
SCE
EXTERNAL
COMPONENTS
V
DD
Fig. 3 Pin 14 SCE
Fig. 2 Pin 11 SSC
SDI
SCI
BIAS
V
DD
SDI
SCI
Fig. 4 Pins 5 - 8 SDI - SCI
522 - 49 - 01
4
GENNUM [ GENNUM CORPORATION ]
