SWF
SSI
V
CC
0µ1
10µ
DV
CC
+5V
V
+5V
+
CC
100
100
3k3
0µ1
0µ1
+
+
10µ
10µ
DGND
100
V
CC
INPUT SELECTION
V
CC
0µ1
SYNC WARNING FLAG
HSYNC OUTPUT
DGND
GND
DGND
DGND
25
ECL
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
390
4
3
2
1 28 27 26
DATA
4
3
2
1
28 27 26
INPUT
390
100
100
100
100
100
100
25
24
23
22
21
20
19
5
6
PD7
PD6
PD5
PD4
PD3
PD2
PD1
SDI
SDI
SCI
SCI
SS1
SS0
SSC
24
23
22
21
20
19
5
SDO
SDO
SCO
SCO
SS1
SS0
CD
DDI
V
CC
6
7
8
DDI
V
7
0µ1
100
100
8
GS9000C
GS9005A
CC2
INPUT
47p
75
100
100
V
SDI
SDI
ƒ/2
V
CC
9
390
390
9
10
11
10
11
100
47p
DV
CC
EE3
75
12 13 14 15 16 17 18
DV
CC
12 13 14 15 16 17 18
910
V
CC
5p6
(1)
0µ1
DGND
22n
113
0µ1
100
100
(2)
10n
DGND
DV
1k2
V
CC
CC
1k2
(3)
50k
0µ1
68k
22n
V
CC
120
DGND
STAR
ROUTED
GS9010A
+
0.1µ
1
16
15
14
13
12
11
10
9
6µ8
STDT
P/N
(2)
2
3
4
5
6
7
8
V
OUT
IN-
CC
6µ8
+
CD
HSYNC
GND
COMP
LF
V
CC
3n3
OSC
ƒ/2
STANDARD TRUTH TABLE
ƒ/2 P/N STANDARD
DLY
V
V
100k
CC
CC
FVCAP
SWF
82n
(2)
0
0
1
1
0
1
0
1
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
0µ68
V
CC
180n
0µ1
SWF
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8µF capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0µF non-polarized capacitor provided that
(a) the 0.68µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
Fig. 11 Application Circuit - Adjustment Free Multi-standard Serial to Parallel Convertor
GS9000C, GS9005A and GS9010A INTERCONNECTIONS
Figure 11 shows an application of the GS9000C in an over a set range until the system is correctly locked. An
adjustment free, multi-standard serial to parallel convertor. automatic fine tuning (AFT) loop maintains the VCO control
This circuit uses the GS9010A Automatic Tuning Sub-system voltage at its centre point through continuous, long term
IC and a GS9005A Serial Digital Receiver. The GS9005A may adjustments of the VCO centre frequency.
bereplacedwithaGS9015AReclockerICifcableequalization
is not required.
During normal operation, the GS9000C Decoder provides
continuous HSYNC pulses which disable the ramp/oscillator
of the GS9010A. This maintains the correct Receiver/
ReclockerVCOfrequency.Whenaninterruptiontotheincoming
data stream is detected by the Receiver/Reclocker, the
Carrier Detect goes LOW and tri-states the AFT loop in order
to maintain the correct VCO frequency for a period of about
2 seconds. This allows the Receiver/Reclocker to rapidly
relock when the signal is re-established.
The GS9010A ATS eliminates the need to manually set or
externallytemperaturecompensatetheReceiverorReclocker
VCO.TheGS9010Acanalsodeterminewhethertheincoming
data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
522 - 49 - 01
7
GENNUM [ GENNUM CORPORATION ]
