** Locate the three 0.10µF decoupling
capacitors as close as possible to the
corresponding pins on the GS9000C.
Chip capacitors are recommended.
+5V
22µ
3 x 100n
HSYNC OUTPUT
**
12
13 18
1
V
V
V
HSYNC
PD0
DD DD DD
17
19
20
21
PARALLEL DATA BIT 0
PARALLEL DATA BIT 1
PARALLEL DATA BIT 2
PARALLEL DATA BIT 3
PARALLEL DATA BIT 4
PARALLEL DATA BIT 5
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
PARALLEL DATA BIT 8
PARALLEL DATA BIT 9
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
DECODER
GS9000C
PDI
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PCLK
SCE
5
6
SDI
SDI
SCI
SCI
SS1
SS0
SSC
SDI
SDI
SCI
SCI
IN
IN
IN
IN
7
8
9
22
23
24
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
10
11
25
27
28
16
14
+5V
100k
820p
V
V
V
SWC SWF
SS SS SS
4
2
26 15
3
10p
SYNC WARNING FLAG
13 x 425Ω
39k
All resistors in ohms,
all capacitors in farads,
unless otherwise specified.
+5V
Fig. 8 GS9000C Test Set-Up
4ƒ
SC
DATA
STREAM
T
R
S
T
T
R
S
With correctly synchronized serial data and clock connected
totheGS9000C, theHSYNCoutput(pin1)willtoggleforeach
HSYNC detected. The Parallel Data bits PD0 through PD9
along with the Parallel Clock can be observed on an
oscilloscope or fed to a logic analyzer. These outputs can
alsobefedthroughasuitableTTLtoECLconvertertodirectly
drive parallel inputs to receiving equipment such as monitors
or digital to analog converters.
ACTIVE VIDEO
& H BLANKING
ACTIVE VIDEO
R
S
& H BLANKING
HSYNC
OUT
4:2:2
DATA
STREAM
E
A
V
E
A
S
S
A
V
H
H
ACTIVE
VIDEO
A
V
BLNK
BLNK
V
In operation, the HSYNC output from the GS9000C decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, just
the time at which it toggles.
HSYNC
OUT
Fig. 9 Operation of HSYNC Output
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to the
output of the first word in the TRS. In the following diagram,
data is indicated in 10 bit Hex.
PCLK
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
PDN
HSYNC
Fig. 10 Operation of HSYNC with Respect to PCLK
522 - 49 - 01
6