欢迎访问ic37.com |
会员登录 免费注册
发布采购

GS9000DCTJ 参数 Datasheet PDF下载

GS9000DCTJ图片预览
型号: GS9000DCTJ
PDF下载: 下载PDF文件 查看货源
内容描述: GENLINX II -TM GS9000D串行数字解码器 [GENLINX II -TM GS9000D Serial Digital Decoder]
分类和应用: 解码器商用集成电路
文件页数/大小: 9 页 / 152 K
品牌: GENNUM [ GENNUM CORPORATION ]
 浏览型号GS9000DCTJ的Datasheet PDF文件第1页浏览型号GS9000DCTJ的Datasheet PDF文件第2页浏览型号GS9000DCTJ的Datasheet PDF文件第3页浏览型号GS9000DCTJ的Datasheet PDF文件第4页浏览型号GS9000DCTJ的Datasheet PDF文件第5页浏览型号GS9000DCTJ的Datasheet PDF文件第6页浏览型号GS9000DCTJ的Datasheet PDF文件第8页浏览型号GS9000DCTJ的Datasheet PDF文件第9页  
** Locate the three 0.10µF decoupling  
capacitors as close as possible to the  
corresponding pins on the GS9000D.  
Chip capacitors are recommended.  
+5V  
22µ  
1
3 x 100n  
HSYNC OUTPUT  
**  
12  
13 18  
V
V
V
HSYNC  
PD0  
DD DD DD  
17  
19  
20  
21  
PARALLEL DATA BIT 0  
PARALLEL DATA BIT 1  
PARALLEL DATA BIT 2  
PARALLEL DATA BIT 3  
PARALLEL DATA BIT 4  
PARALLEL DATA BIT 5  
PARALLEL DATA BIT 6  
PARALLEL DATA BIT 7  
PARALLEL DATA BIT 8  
PARALLEL DATA BIT 9  
PARALLEL CLOCK OUT  
SYNC CORRECTION ENABLE  
DECODER  
GS9000D  
PDI  
PD2  
PD3  
PD4  
PD5  
PD6  
PD7  
PD8  
PD9  
PCLK  
5
6
SDI  
SDI  
SDI  
SCI  
SCI  
IN  
IN  
IN  
IN  
SDI  
SCI  
SCI  
SS1  
SS0  
SSC  
7
8
9
22  
23  
24  
STANDARDS SELECT BIT 1  
STANDARDS SELECT BIT 0  
10  
11  
25  
27  
28  
16  
14  
+5V  
100k  
820p  
SCE  
SWC SWF  
V
V
V
SS SS SS  
4
2
26 15  
3
10p  
SYNC WARNING FLAG  
13 x 425  
39k  
All resistors in ohms,  
all capacitors in farads,  
unless otherwise specified.  
+5V  
Fig. 8 GS9000D Test Set-Up  
With synchronized serial data and clock connected to the  
GS9000D, the HSYNC output (pin 1) will toggle for each  
HSYNC detected. The Parallel Data bits PD0 through PD9  
and the Parallel Clock can be observed on an oscilloscope  
or fed to a logic analyzer. To directly drive parallel inputs to  
receiving equipment, such as monitors or digital to analog  
converters, these outputs can be fed through a suitable TTL  
to ECL converter.  
The HSYNC output toggles to indicate the presence of the  
TRS on the falling edge of PCLK, one data symbol prior to  
the output of the first word in the TRS. In the following  
diagram, data is indicated in 10-bit Hex.  
PCLK  
XXX 3FF 000 000 XXX  
XXX 3FF 000 000 XXX  
PDN  
In operation, the HSYNC output from the GS9000D decoder  
toggles on each occurrence of the timing reference signal  
(TRS). The state of the HSYNC output is not significant, but  
the time at which it toggles is significant.  
HSYNC  
Fig. 10 Operation of HSYNC with Respect to PCLK  
4ƒ  
DATA  
STREAM  
T
R
S
T
R
S
T
R
S
SC  
ACTIVE VIDEO  
& H BLANKING  
ACTIVE VIDEO  
& H BLANKING  
HSYNC  
OUT  
4:2:2  
DATA  
STREAM  
E
A
V
E
S
A
V
S
A
V
H
BLNK  
H
BLNK  
ACTIVE  
VIDEO  
A
V
HSYNC  
OUT  
Fig. 9 Operation of HSYNC Output  
7 of 9  
GENNUM CORPORATION  
18784 - 3