GS4915 Data Sheet
Table 3-5: Output Behaviour in Manual Bypass Mode
FCTRL[1:0]
Input
DOUBLE
LOCK
Output
Auto [00]
27MHz
74.25MHz
148.5MHz
Other
X
X
X
X
X
X
X
X
0
HIGH*
HIGH*
HIGH*
LOW
27MHz
74.25MHz
148.5MHz
Input
Fixed – 27MHz
[01]
27MHz
HIGH*
LOW
27MHz
74.25MHz
148.5MHz
Other
74.25MHz
148.5MHz
Input
LOW
LOW
Fixed –
27MHz
LOW
27MHz
74.25MHz [10]
74.25MHz
148.5MHz
Other
0
HIGH*
LOW
74.25MHz
148.5MHz
Input
0
0
LOW
Fixed –
148.5MHz [11]
27MHz
X
X
X
X
LOW
27MHz
74.25MHz
148.5MHz
Other
LOW
74.25MHz
148.5MHz
Input
HIGH*
LOW
*NOTE: Although LOCK = HIGH under these conditions, the output clock will be a copy of the
selected input clock and will have the jitter of the input clock.
Table 3-6: Output Behaviour in Forced Output Mode
FCTRL[1:0]
Input
DOUBLE
LOCK
Output
Auto [00]
27MHz
X
0
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
27MHz
74.25MHz
148.5MHz
148.5MHz
Last locked*
27MHz
74.25MHz
1
148.5MHz
Other
X
X
X
X
X
X
Fixed – 27MHz
[01]
27MHz
74.25MHz
148.5MHz
Other
27MHz
27MHz
27MHz
39145 - 3 November 2007
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