GS4915 Data Sheet
Auto Frequency Mode
When FCTRL[1:0] = 00, the device will operate in Auto Frequency mode. In this
mode, the GS4915 will automatically clean the selected input clock if its frequency
is found to be contained in any of the ranges listed above.
The LOCK output pin will be HIGH whenever the device has successfully locked
its cleaning PLL to the selected input clock. In Auto Frequency mode, LOCK will be
HIGH if the input clock frequency is 27MHz ± 0.4%, 74.25MHz ± 0.4%, or
148.5MHz ± 0.4%.
If the input clock varies by more than ± 6.4%, the LOCK output pin will be LOW.
Between 0.4% and 6.4%, the device may lock or bypass, as shown in Figure 3-1.
Frequencies in this range should not be applied to the device.
+6.4%
+0.4%
-0.4%
-6.4%
Locked
Undefined
Unlocked
Figure 3-1: Locked, Undefined and Unlocked regions
Fixed Frequency Mode
When FCTRL[1:0] ≠ 00, the device will operate in Fixed Frequency mode. In this
mode, the device will only clean the selected input clock if its frequency is found to
be in the range defined by the particular setting of the FCTRL[1:0] pins.
For example, if FCTRL[1:0] = 01, the GS4915 will only clean the input clock if its
frequency is 27MHz ± 0.4%; if FCTRL[1:0] = 10, the GS4915 will only clean the
input clock if its frequency is 74.25MHz ± 0.4%; and if FCTRL[1:0] = 11, the
GS4915 will only clean the input clock if its frequency is 148.5MHz ± 0.4%.
In Fixed Frequency mode, the LOCK output pin will be set HIGH after the device
has locked its cleaning PLL to the selected input clock, and only if the input clock
frequency matches the frequency selected by the setting of the FCTRL[1:0] pins.
Otherwise, LOCK will be LOW.
39145 - 3 November 2007
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GENNUM [ GENNUM CORPORATION ]
