GS4901B/GS4900B Preliminary Data Sheet
Total Field
10FID Output
Horizontal Sync Output
Line 1 every n frames where:
n = 5 @ 29.97 fps, 30 fps
n = 10 @ 59.94 fps, 60 fps
Figure 3-7: Optional 10FID Output Timing
The phasing of the divide by n frame counter may be reset by an external pulse on
the 10FID input pin, or via register 1Ah of the host interface (see Section 3.10.3 on
page 66).
NOTE: If a 10FID input signal is not provided to the device, the 10FID output signal
will be invalid until the user initiates a reset via the host interface. The user should
also reset the 10FID signal via the host if at any time the H input reference signal
is removed and then re-applied.
3.8.2 Audio Frame Synchronizing Pulse (GS4901B only)
As described in Table 1-3, the audio frame synchronizing (AFS) pulse identifies the
frame, within an n frame sequence, in which the audio sample rate clock is aligned
with the H Sync of line 1. It is generated for all video formats.
The leading edge of the AFS output pulse is co-timed with the H Sync
th
corresponding to line 1 of every n frame in the sequence, and therefore identifies
the exact time at which the audio sample rate clock and video PCLK have
synchronous leading edges.
The number of frames in the sequence, n, is determined by the video frame rate
and the audio clock frequency. These are selected using the VID_STD[5:0] and
ASR_SEL[2:0] pins or via the host interface.
By default, the AFS pulse is 1 line long, as shown in Figure 3-8. Alternatively, by
setting bit 1 of the Audio_Control register, the AFS output signal may be configured
to go HIGH on the leading edge of the H Sync pulse of line 1 of the first field in the
‘n’ frame sequence, and be reset LOW on the leading edge of the H Sync pulse of
line 1 of the second field in the sequence. The AFS timing in this configuration is
similar to the 10FID optional timing shown in Figure 3-7.
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