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GS4900B 参数 Datasheet PDF下载

GS4900B图片预览
型号: GS4900B
PDF下载: 下载PDF文件 查看货源
内容描述: SD时钟和定时发生器与同步锁相 [SD Clock and Timing Generator with GENLOCK]
分类和应用: 时钟
文件页数/大小: 95 页 / 1369 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS4901B/GS4900B Preliminary Data Sheet  
3.8 Video Timing Generator  
The internal PCLK signal generated by the clock synthesis circuit is used to  
produce horizontal, vertical, and frame based timing output signals.  
The signals generated and available to the application layer via the TIMING_OUT  
pins are: H Sync, H Blanking, V Sync, V Blanking, F Sync, F Digital, DE, 10FID,  
AFS (GS4901B only), and USER_1~4. These signals are defined in Section 1.5 on  
page 24. Additional information pertaining to the 10FID, AFS, and USER_1~4  
signals can be found in the sub-sections below.  
When the GS4901B/GS4900B is operating in Genlock mode, the H, V, and F  
based output timing signals are synchronized to the H, V, and F reference signals  
applied to the inputs by the application layer. The video timing outputs may be  
offset from the input reference by programming the Genlock Offset registers  
beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 35).  
All TIMING_OUT signals have selectable polarity. The default polarities for each  
signal are given in the descriptions in Section 1.5 on page 24.  
3.8.1 10 Field ID Pulse  
As described in Table 1-3, the 10 field ID (10FID) output signal is used in the  
identification of film to video cadence. It is only generated for 29.97, 30, 59.94, and  
60fps formats.  
th  
The 10FID pulse is generated on every 5 frame for 29.97 and 30fps formats, and  
th  
every 10 frame on 59.94 and 60fps formats.  
By default, the 10FID signal is set HIGH on the leading edge of the H Sync output  
for the duration of line 1 of field 1 at the start of the 10 field sequence. This is shown  
in Figure 3-6.  
Alternatively, by setting bit 4 of the Video_Control register at address 4Ch of the  
host interface, the 10FID output signal may be configured to go HIGH (default  
polarity) on the leading edge of the H Sync pulse of line 1 of the first field in the 10  
field sequence, and be reset LOW on the leading edge of the H Sync pulse of line  
1 of the second field in the 10 field sequence. This is shown in Figure 3-7.  
Total Line  
10FID Output  
Line 1, Frame 1 every 'n' frames  
Horizontal Sync Output  
Line 1 every n frames where:  
n = 5 @ 29.97 fps, 30 fps  
n = 10 @ 59.94 fps, 60 fps  
Figure 3-6: Default 10FID Output Timing  
37703 - 0 April 2006  
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